CY7C1381D, CY7C1381F
CY7C1383D, CY7C1383F
Identification Register Definitions
Instruction Field
CY7C1381D/CY7C1381F CY7C1383D/CY7C1383F
(512K × 36)
(1M × 18)
Description
Revision Number (31:29)
Device Depth (28:24) [13]
000
01011
000
01011
Describes the version number.
Reserved for internal use.
Device Width (23:18) 119-BGA
101001
101001
Defines the memory type and
architecture.
Device Width (23:18) 165-FBGA
000001
000001
Defines the memory type and
architecture.
Cypress Device ID (17:12)
100101
010101
Defines the width and density.
Cypress JEDEC ID Code (11:1)
00000110100
00000110100
Allows unique identification of SRAM
vendor.
ID Register Presence Indicator (0)
1
1
Indicates the presence of an ID
register.
Scan Register Sizes
Register Name
Instruction Bypass
Bypass
ID
Boundary Scan Order (119-ball BGA package)
Boundary Scan Order (165-ball fBGA package)
Bit Size (×36)
3
1
32
85
89
Bit Size (×18)
3
1
32
85
89
Identification Codes
Instruction
EXTEST
Code
000
IDCODE
001
SAMPLE Z
010
RESERVED
011
SAMPLE/PRELOAD
100
RESERVED
101
RESERVED
110
BYPASS
111
Description
Captures Input/Output ring contents. Places the boundary scan register between TDI and
TDO. Forces all SRAM outputs to High-Z state.
Loads the ID register with the vendor ID code and places the register between TDI and TDO.
This operation does not affect SRAM operations.
Captures Input/Output ring contents. Places the boundary scan register between TDI and
TDO. Forces all SRAM output drivers to a High-Z state.
Do Not Use. This instruction is reserved for future use.
Captures Input/Output ring contents. Places the boundary scan register between TDI and
TDO. Does not affect SRAM operation.
Do Not Use. This instruction is reserved for future use.
Do Not Use. This instruction is reserved for future use.
Places the bypass register between TDI and TDO. This operation does not affect SRAM
operations.
Note:
13. Bit #24 is “1” in the register definitions for both 2.5V and 3.3V versions of this device.
Document #: 38-05544 Rev. *F
Page 15 of 29
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