CY7C1383D-100AXC 데이터 시트보기 (PDF) - Cypress Semiconductor
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CY7C1383D-100AXC Datasheet PDF : 29 Pages
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CY7C1381D, CY7C1381F
CY7C1383D, CY7C1383F
Switching Characteristics
Over the Operating Range [20, 21]
Parameter
tPOWER
Clock
tCYC
tCH
tCL
Output Times
tCDV
tDOH
tCLZ
tCHZ
tOEV
tOELZ
tOEHZ
Setup Times
tAS
tADS
tADVS
tWES
tDS
tCES
Hold Times
tAH
tADH
tWEH
tADVH
tDH
tCEH
Description
VDD(Typical) to the first Access [22]
Clock Cycle Time
Clock HIGH
Clock LOW
Data Output Valid After CLK Rise
Data Output Hold After CLK Rise
Clock to Low-Z [23, 24, 25]
Clock to High-Z [23, 24, 25]
OE LOW to Output Valid
OE LOW to Output Low-Z [23, 24, 25]
OE HIGH to Output High-Z [23, 24, 25]
Address Setup Before CLK Rise
ADSP, ADSC Setup Before CLK Rise
ADV Setup Before CLK Rise
GW, BWE, BW[A:D] Setup Before CLK Rise
Data Input Setup Before CLK Rise
Chip Enable Setup
Address Hold After CLK Rise
ADSP, ADSC Hold After CLK Rise
GW, BWE, BW[A:D] Hold After CLK Rise
ADV Hold After CLK Rise
Data Input Hold After CLK Rise
Chip Enable Hold After CLK Rise
133 MHz
Min
Max
1
7.5
2.1
2.1
6.5
2.0
2.0
0
4.0
3.2
0
4.0
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
100 MHz
Min
Max
Unit
1
ms
10
ns
2.5
ns
2.5
ns
8.5
ns
2.0
ns
2.0
ns
0
5.0
ns
3.8
ns
0
ns
5.0
ns
1.5
ns
1.5
ns
1.5
ns
1.5
ns
1.5
ns
1.5
ns
0.5
ns
0.5
ns
0.5
ns
0.5
ns
0.5
ns
0.5
ns
Notes:
20. Timing reference level is 1.5V when VDDQ = 3.3V and is 1.25V when VDDQ = 2.5V.
21. Test conditions shown in (a) of AC Test Loads unless otherwise noted.
22. This part has a voltage regulator internally; tPOWER is the time that the power needs to be supplied above VDD(minimum) initially, before a read or write operation
can be initiated.
23. tCHZ, tCLZ,tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of AC Test Loads and Waveforms on page 19. Transition is measured ± 200
mV from steady-state voltage.
24. At any given voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to
achieve High-Z prior to Low-Z under the same system condition.
25. This parameter is sampled and not 100% tested.
Document #: 38-05544 Rev. *F
Page 20 of 29
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