S34ML01G204THB000 데이터 시트보기 (PDF) - Spansion Inc.
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S34ML01G204THB000 Datasheet PDF : 79 Pages
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Data Sheet
1.7 Mode Selection
Table 1.6 Mode Selection
Mode
CLE
ALE
CE#
Read Mode
Command Input
High
Low
Low
Address Input
Low
High
Low
Command Input
High
Low
Low
Program or Erase Mode
Address Input
Low
High
Low
Data Input
Low
Low
Low
Data Output (on going)
Low
Low
Low
Data Output (suspended)
X
X
X
Busy Time in Read
X
X
X
Busy Time in Program
X
X
X
Busy Time in Erase
X
X
X
Write Protect
X
X
X
Stand By
X
X
High
Notes:
1. X can be VIL or VIH. High = Logic level high, Low = Logic level low.
2. WP# should be biased to CMOS high or CMOS low for stand-by mode.
3. During Busy Time in Read, RE# must be held high to prevent unintended data out.
WE#
Rising
Rising
Rising
Rising
Rising
High
High
High
X
X
X
X
RE#
High
High
High
High
High
Falling
High
High (3)
X
X
X
X
WP#
X
X
High
High
High
X
X
X
High
High
Low
0V / VCC (2)
2. Bus Operation
There are six standard bus operations that control the device: Command Input, Address Input, Data Input,
Data Output, Write Protect, and Standby. (See Table 1.6.)
Typically glitches less than 5 ns on Chip Enable, Write Enable, and Read Enable are ignored by the memory
and do not affect bus operations.
2.1
Command Input
The Command Input bus operation is used to give a command to the memory device. Commands are
accepted with Chip Enable low, Command Latch Enable high, Address Latch Enable low, and Read Enable
high and latched on the rising edge of Write Enable. Moreover, for commands that start a modify operation
(program/erase) the Write Protect pin must be high. See Figure 6.1 on page 45 and Table 5.4 on page 42 for
details of the timing requirements. Command codes are always applied on I/O7:0 regardless of the bus
configuration (x8 or x16).
2.2
Address Input
The Address Input bus operation allows the insertion of the memory address. For the S34ML02G2 and
S34ML04G2 devices, five write cycles are needed to input the addresses. For the S34ML01G2, four write
cycles are needed to input the addresses. If necessary, a 5th dummy address cycle can be issued to
S34ML01G2, which will be ignored by the NAND device without causing problems. Addresses are accepted
with Chip Enable low, Address Latch Enable high, Command Latch Enable low, and Read Enable high and
latched on the rising edge of Write Enable. Moreover, for commands that start a modify operation (program/
erase) the Write Protect pin must be high. See Figure 6.2 on page 46 and Table 5.4 on page 42 for details of
the timing requirements. Addresses are always applied on I/O7:0 regardless of the bus configuration (x8 or
x16). Refer to Table 1.3 through Table 1.5 on page 19 for more detailed information.
20
Spansion® SLC NAND Flash Memory for Embedded
S34ML01G2_04G2_10 September 5, 2014
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