SC16IS740 데이터 시트보기 (PDF) - NXP Semiconductors.

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SC16IS740

Single UART with I2C-bus/SPI interface, 64 bytes of transmit and receive FIFOs, IrDA SIR built-in support

NXP Semiconductors. 

NXP Semiconductors

SC16IS740/750/760

Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

voltage

(V)

oscillator starts

XTAL1 VIH

stable clocks

0V

tstartup

Fig 12. Start-up time

time (ms)

002aaf521

7.5 Interrupts

The SC16IS740/750/760 has interrupt generation and prioritization (seven prioritized

levels of interrupts) capability. The interrupt enable registers (IER and IOIntEna) enable

each of the seven types of interrupts and the IRQ signal in response to an interrupt

generation. When an interrupt is generated, the IIR indicates that an interrupt is pending

and provides the type of interrupt through IIR[5:0]. Table 6 summarizes the interrupt

control functions.

Table 6.

IIR[5:0]

00 0001

00 0110

00 1100

00 0100

00 0010

00 0000

11 0000

01 0000

10 0000

Summary of interrupt control functions

Priority Interrupt type

level

Interrupt source

none

none

none

1

receiver line status OE, FE, PE, or BI errors occur in characters in the

RX FIFO

2

RX time-out

Stale data in RX FIFO

2

RHR interrupt

Receive data ready (FIFO disable) or

RX FIFO above trigger level (FIFO enable)

3

THR interrupt

Transmit FIFO empty (FIFO disable) or

TX FIFO passes above trigger level (FIFO enable)

4

modem status[1]

Change of state of modem input pins

5

I/O pins[1]

Input pins change of state

6

Xoff interrupt

Receive Xoff character(s)/ special character

7

CTS, RTS

RTS pin or CTS pin change state from active (LOW)

to inactive (HIGH)

[1] Available only on SC16IS750/SC16IS760.

It is important to note that for the framing error, parity error, and break conditions, LSR[7]

generates the interrupt. LSR[7] is set when there is an error anywhere in the RX FIFO,

and is cleared only when there are no more errors remaining in the FIFO. LSR[4:2] always

represent the error status for the received character at the top of the RX FIFO. Reading

the RX FIFO updates LSR[4:2] to the appropriate status for the new character at the top of

the FIFO. If the RX FIFO is empty, then LSR[4:2] are all zeros.

For the Xoff interrupt, if an Xoff flow character detection caused the interrupt, the interrupt

is cleared by an Xon flow character detection. If a special character detection caused the

interrupt, the interrupt is cleared by a read of the IIR.

SC16IS740_750_760

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 7 — 9 June 2011

© NXP B.V. 2011. All rights reserved.

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