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SC16IS740

Single UART with I2C-bus/SPI interface, 64 bytes of transmit and receive FIFOs, IrDA SIR built-in support

NXP Semiconductors. 

NXP Semiconductors

SC16IS740/750/760

Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

7.8 Programmable baud rate generator

The SC16IS740/750/760 UART contains a programmable baud rate generator that takes

any clock input and divides it by a divisor in the range between 1 and (216 – 1). An

additional divide-by-4 prescaler is also available and can be selected by MCR[7], as

shown in Figure 15. The output frequency of the baud rate generator is 16  the baud

rate. The formula for the divisor is given in Equation 1:

 -X----T---A----L----1-----c---r---y---ps---tr--a-e--l-s--c-i--na---p-l--e-u--r-t----f--r--e----q---u---e---n----c---y-

divisor = ---------------d---e---s---i--r---e---d-----b---a----u---d-----r---a---t--e---------1---6----------------

(1)

where:

prescaler = 1, when MCR[7] is set to ‘0’ after reset (divide-by-1 clock selected)

prescaler = 4, when MCR[7] is set to ‘1’ after reset (divide-by-4 clock selected).

Remark: The default value of prescaler after reset is divide-by-1.

Figure 15 shows the internal prescaler and baud rate generator circuitry.

XTAL1

XTAL2

INTERNAL

OSCILLATOR

LOGIC

PRESCALER

LOGIC

(DIVIDE-BY-1)

input clock

PRESCALER

LOGIC

(DIVIDE-BY-4)

MCR[7] = 0

reference

clock

MCR[7] = 1

BAUD RATE

GENERATOR

LOGIC

internal

baud rate

clock for

transmitter

and receiver

002aaa233

Fig 15. Prescaler and baud rate generator block diagram

DLL and DLH must be written to in order to program the baud rate. DLL and DLH are the

least significant and most significant byte of the baud rate divisor. If DLL and DLH are both

zero, the UART is effectively disabled, as no baud clock will be generated.

Remark: The programmable baud rate generator is provided to select both the transmit

and receive clock rates.

Table 7 and Table 8 show the baud rate and divisor correlation for crystal with frequency

1.8432 MHz and 3.072 MHz, respectively. The crystal’s frequency tolerance should be

selected as such to keep the baud rate error to be below 1 % for reliable operation with

other UARTs. Crystals with 100 ppm is generally recommended.

Figure 16 shows the crystal clock circuit reference.

SC16IS740_750_760

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 7 — 9 June 2011

© NXP B.V. 2011. All rights reserved.

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