DS2430A 데이터 시트보기 (PDF) - Maxim Integrated

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DS2430A

256-Bit 1-Wire EEPROM

Maxim Integrated 

DS2430A

PARAMETER SYMBOL

CONDITIONS

MIN TYP MAX UNITS

EEPROM

Programming Current

IPROG

(Notes 5, 18)

0.5

mA

Programming Time

tPROG

(Note 19)

10

ms

Write/Erase Cycles (En-

durance) (Notes 20, 21)

S Data Retention (Notes 22,

23, 24)

NCY

At 25°C

At 85°C (worst case)

tDR

At 85°C (worst case)

200k

50k

40



years

N Note 1:

G Note 2:

I Note 3:

DES Note 4:

Specifications at TA = -40°C are guaranteed by design only and not production-tested.

System requirement.

Maximum allowable pullup resistance is a function of the number of 1-Wire devices in the system and 1-Wire

recovery times. The specified value here applies to systems with only one device and with the minimum tREC. For

more heavily loaded systems, an active pullup such as that found in the DS2482-x00, DS2480B, or DS2490 may

be required. If longer tREC is used, higher RPUP values may be able to be tolerated.

Maximum value represents the internal parasite capacitance when VPUP is first applied. If a 2.2k resistor is used

Note 5:

Note 6:

Note 7:

Note 8:

Note 9:

Note 10:

Note 11:

Note 12:

Note 13:

Note 14:

Note 15:

Note 16:

Note 17:

Note 18:

Note 19:

Note 20:

Note 21:

Note 22:

to pull up the data line, 2.5µs after VPUP has been applied the parasite capacitance will not affect normal

communications.

Guaranteed by design, characterization and/or simulation only. Not production tested.

W VTL, VTH, and VHY are a function of the internal supply voltage which is itself a function of VPUP, RPUP, 1-Wire

E timing, and capacitive loading on DATA. Lower VPUP, higher RPUP, shorter tREC, and heavier capacitive loading

all lead to lower values of VTL, VTH, and VHY.

N Voltage below which, during a falling edge on DATA, a logic 0 is detected.

The voltage on DATA needs to be less or equal to VIL(MAX) at all times the master is driving DATA to a logic-0

level.

R Voltage above which, during a rising edge on DATA, a logic 1 is detected.

O After VTH is crossed during a rising edge on DATA, the voltage on DATA has to drop by at least VHY to be

detected as logic '0'.

F The I-V characteristic is linear for voltages less than 1V.

Applies to a single device attached to a 1-Wire line.

The earliest recognition of a negative edge is possible at tREH after VTH has been reached on the preceding rising

D edge.

E Defines maximum possible bit rate. Equal to 1/(tW0L(min) + tREC(min)).

Interval after tRSTL during which a bus master is guaranteed to sample a logic-0 on DATA if there is a DS2430A

D present. Minimum limit is tPDH(max); maximum limit is tPDH(min) + tPDL(min).

 in Figure 10 represents the time required for the pullup circuitry to pull the voltage on DATA up from VIL to

N VTH. The actual maximum duration for the master to pull the line low is tW1Lmax + tF and tW0Lmax + tF respectively.

E  in Figure 10 represents the time required for the pullup circuitry to pull the voltage on DATA up from VIL to the

input high threshold of the bus master. The actual maximum duration for the master to pull the line low is

M tRLmax + tF.

Current drawn from DATA during the EEPROM programming interval. The pullup circuit on DATA during the

programming interval should be such that the voltage drop been VPUP and DATA is less than 0.25V. Current

M increases with increased VPUP.

O Interval begins tREHmax after the trailing rising edge on DATA for the last timeslot of the validation key for a valid

copy sequence. Interval ends once the device's self-timed EEPROM programming cycle is complete and the

C current drawn by the device has returned from IPROG to IL.

Write-cycle endurance is degraded as TA increases.

E Not 100% production-tested; guaranteed by reliability monitor sampling.

RData retention is degraded as TA increases.

Note 23:

NOT Note 24:

Guaranteed by 100% production test at elevated temperature for a shorter time; equivalence of this production

test to data sheet limit at operating temperature range is established by reliability testing.

EEPROM writes can become nonfunctional after the data-retention time is exceeded. Long-term storage at

elevated temperatures is not recommended; the device can lose its write capability after 10 years at +125°C or 40

years at +85°C.

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