STI5512 데이터 시트보기 (PDF) - STMicroelectronics

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STI5512

SET TOP BOX BACKEND DECODER WITH INTEGRATED HOST PROCESSOR

STMicroelectronics 

CONFIDENTIAL STi5512

2 Architecture overview

A block diagram of a DVB digital set top receiver is shown in Figure 1 below.

The STi5512 includes the following hardware modules:

• Transport demultiplexor

• System microcontroller

• MPEG video decoder

• MPEG audio decoder

• PAL/NTSC/SECAM encoder

The STi5512 directly interfaces to external memory and peripherals with no extra glue logic, keeping the system cost to

a minimum. The STi5512 architectural block diagram is shown below.

Antenna/cable

I2C bus

DRAM

Flash

ROM

1 or 2

4M x 16 bit SDRAM

Polarity

I2C

Tuner A/D

I2C (SSC)

Buffers PIO

I2C

Link-IC

port

Link-IC

EMI

SDEMRAI MCRVGBSB

STi5512

PCM

PIO

PIO

UART 1284 UART

SmartCard

power

control

UART

Video

DAC

Modulator

Audio

Audio

amplifier

PCMCIA

CA module

SmartCard

(x2)

Modem

High speed

(IEEE 1284)

and low speed

data ports

Figure 1 Digital set top box block diagram

7110123 B

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