MST705 데이터 시트보기 (PDF) - Mstar Semiconductor

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MST705

Small Size LCD TV Processor with Video Decoder

Mstar Semiconductor 

MST705

Small Size LCD TV Processor with Video Decoder

Preliminary Data Sheet Version 0.1

Scaler Register (Bank=00, Registers 01h ~ 9Fh)

Index Name

Bits Description

2Bh

OPL_SPAN

7:0 Default : 0x00

Access : R/W, DB

READ_FRAME

7 0: OPL_SET stores line-based value.

1: OPL_SET stores frame-based value.

OPL_SPAN[14:8]

6:0 See description for OPL_SPAN[7:0].

2Ch ~ -

2Fh

-

7:0 Default : -

7:0 Reserved.

Access : -

30h

HSR_L

7:0 Default : 0x00

Access : R/W

HSR [7:0]

7:0 Horizontal Scaling ratio (20 bits fraction) for scaling down 1/2^20

to (2^20-1)/2^20 (lower 8 bits).

31h

HSR_M

7:0 Default : 0x00

Access : R/W

HSR[15:8]

7:0 Horizontal Scaling ratio (20 bits fraction) for scaling down 1/2^20

to (2^20-1)/2^20 (middle 8 bits).

Mstar Confidential 32h

HSR_H

HS_EN

7:0 Default : 0x00

7 Horizontal Scaling Enable.

Access : R/W

0: Disable.

for 深圳市江启科技有限公司 CBILINEAR_EN

1: Enable.

6 Complemental Bi-Linear Enable.

Internal Use Only FORCEBICOLOR

5 0: Chrominance using same setting as Luminance defined by

CBILINEAR.

1: Chrominance always using bi-linear algorithm.

-

4 Reserved.

HSR[19:16]

3:0 Horizontal Scaling Ratio (20 bits fraction) for scaling down 1/2^20

to (2^20-1)/2^20 (higher 8 bits).

33h

VSR_L

7:0 Default : 0x00

Access : R/W

VSR[7:0]

7:0 Vertical Scaling ratio (2 bits integer, 20 bits fraction) for scaling

down to 1/2.9999 (lower 8 bits).

xx.xxxxxxxxxxxxxxxxxxxx

34h

VSR_M

7:0 Default : 0x00

Access : R/W

VSR[15:8]

7:0 Vertical Scaling ratio (2 bits integer, 20 bits fraction) for scaling

down to 1/2.9999 (middle 8 bits).

xx.xxxxxxxxxxxxxxxxxxxx

35h

VSR_H

7:0 Default : 0x00

Access : R/W

VS_EN

7 Vertical Scaling Enable.

0: Disable.

1: Enable.

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Copyright © 2010 MStar Semiconductor, Inc. All rights reserved.

11/2/2010

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