ISL12022MA 데이터 시트보기 (PDF) - Intersil

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ISL12022MA

Low Power RTC with Battery Backed SRAM, Integrated ±5ppm Temperature Compensation and Auto Daylight Saving

Intersil 

ISL12022MA

SDA vs SCL Timing

tF

tHIGH

tLOW

tR

SCL

tSU:STA

SDA

(INPUT TIMING)

SDA

(OUTPUT TIMING)

tSU:DAT

tHD:STA

tHD:DAT

tAA tDH

tSU:STO

tBUF

EQUIVALENT AC OUTPUT LOAD CIRCUIT FOR VDD = 5V

5.0V

SDA

AND

IRQ/FOUT

1533Ω

FOR VOL= 0.4V

AND IOL = 3mA

100pF

FIGURE 1. STANDARD OUTPUT LOAD FOR TESTING

THE DEVICE WITH VDD = 5.0V

Symbol Table

WAVEFORM

INPUTS

Must be steady

OUTPUTS

Will be steady

May change

from LOW

to HIGH

May change

from HIGH

to LOW

Don’t Care:

Changes Allowed

Will change

from LOW

to HIGH

Will change

from HIGH

to LOW

Changing:

State Not Known

N/A

Center Line is

High Impedance

8

FN7575.1

July 9, 2010

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