Line
Voltage
LD7577JA
pulled low to maintain in a off-state no matter the gate
resistor is disconnected or opened in any case.
V BNO
4.16
3.92
1.05V
Vcc
UVLO- ON
UVLO- OFF
AC OK area
OUT
Switching
Non- Switching
Fig.21
t
t
AC OK area
t
Switching
t
Pull-Low Resistor on the Gate Pin of
MOSFET
An anti-floating resistor is implemented in the OUT pin to
prevent any uncertain output, which may cause MOSFET
to work abnormally or false trigger on. However, such
design may not apply in all the disconnection of gate
resistor RG. It is still strongly recommended to have a
resistor connected at the MOSFET gate terminal (as
shown in figure 22) to provide extra protection in fault
conditions.
This external pull-low resistor is to prevent the MOSFET
from being damaged during power-on when the gate
resistor is disconnected. In such single-fault condition,
as shown in figure 23, the resistor R8 can provide a
discharge path to avoid the MOSFET from being
false-triggered by the coupling through the gate-to-drain
capacitor CGD. Therefore, the MOSFET gate should be
Fig. 22
i = Cgd ⋅ dVbulk
dt
Fig. 23
Leadtrend Technology Corporation
LD7577JA-DS-00b August 2010
14
www.leadtrend.com.tw