TECHNICAL INFORMATION
Application / Test Circuit
CI
2.2uF
+
RF
20KΩ
RI
20KΩ
VP1 10
IN1 11
CA
0.1uF
BIASCAP 16
(Pin 8)
5V
5V
MUTE 12
TA2024
Processing
&
Modulation
CI
2.2uF
+
20KRΩF
RI
20KΩ
VP2 14
IN2 15
6
(Pin 8) 8.25KΩR, 1R%EF
3
REF
DCAP1
+12V
1meg Ω
CD
0.1uF
0.1uF
To Pin 1
CS
0.1uF
CS
0.1uF
2 DCAP2
18 SLEEP
4 V5D
5 AGND1
9 V5A
8 AGND2
17 AGND3
Processing
&
Modulation
5V
13
21
23
NC
32
34
VDD1
31 OUTP1
Lo
10uH, 2A
PGND1
VDD1
DO
(Pin 35)
(Pin 35)
28 OUTM1
10uLHo, 2A
*Co
0.47uF
*0C.4o7uF
CZ
0.47uF
RZ
10Ω, 1/2W
CCM
0.1uF
PGND1
19
7
VDD2
DO
(Pin 35)
FAULT
OVERLOADB
24 OUTP2
Lo
10uH, 2A
PGND2
VDD2
DO
(Pin 20)
(Pin 20)
27 OUTM2 10uLHo, 2A
*Co
0.47uF
CZ
0.47uF
*Co
0.47uF
RZ
10Ω, 1/2W
C0.C1MuF
PGND2
DO
(Pin 20)
CPUMP 36
VDDA 33
DGND 22
+5VGEN 1
VDD1 30
VDD1 29
PGND1 35
VDD2 25
VDD2 26
PGND2 20
+ 1CuPF
CS
0.1uF
0C.S1uF
To Pins 4,9
CSW
0.1uF
+ CSW
180uF, 16V
VDD (+12V)
CSW
0.1uF
+ CSW
180uF, 16V
RL
4Ω or *8Ω
4Ω oRrL*8Ω
Note: Analog and Digital/Power Grounds must
be connected locally at the TA2024
Analog Ground
Digital/Power Ground
All Diodes Motorola MBRS130T3
* Use Co = 0.22µF for 8 Ohm loads
TA2024 Preliminary, Rev. 1.0
Page 5