7442 데이터 시트보기 (PDF) - SANYO -> Panasonic

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7442

PIP Controller

SANYO -> Panasonic 

LC7442, 7442E

Initial Settings

• RES pin: reset

This pin must be held low when power is first applied.

Power supply (DVDD, AVDD, OVDD, KVDD)

RES

tD: At least a few microseconds.

• Internal control registers

The table below lists the states of the registers following a reset.

Register

SBY

KOUT–A, KOUT–B

PLL6

PLL5

PLL4

PLL3

State

H

L

L

L

H

H

Notes: H: VDD level

L: VSS level

These states are set even if SBY = H.

Since all system operations are stopped at this time, the data held in external

memory cannot be retained.

Registers other than the above are not initialized by a reset.

Serial Data Interface

• Serial input format

The first 8 bits of data following SDE going low specify an address, and the next 8 bits are register data for that address.

The last 8 bits of data are transferred to the incremented address.

The address can be re-specified after switching SDE from low to high to low again (

).

Since the PLL clock is not used for serial data transfer, data transfers can be performed when SBY is high. However,

data cannot be transferred to registers that are initialized by a reset.

Since there is no way to confirm that the transferred data was latched correctly, we recommend refreshing this data

periodically.

No. 4412-18/22

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