BR24C01A-W 데이터 시트보기 (PDF) - ROHM Semiconductor
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BR24C01A-W Datasheet PDF : 13 Pages
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Memory ICs
BR24C01A-W / BR24C01AF-W / BR24C01AFJ-W / BR24C01AFV-W / BR24C02-W / BR24C02F-W /
BR24C02FJ-W / BR24C02FV-W / BR24C04-W / BR24C04F-W / BR24C04FJ-W / BR24C04FV-W
When data is being read from the IC, eight bits of data (read data) are output and the IC waits for a returned LOW
acknowledge signal (ACK signal). When an acknowledge signal (ACK signal) is detected and a stop condition is not
sent from the master (µ-COM) side, the IC continues to output data. If an acknowledge signal (ACK signal) is not
detected, the IC interrupts the data transfer and ceases reading operations after recognizing the stop condition (stop
bit). The IC then enters the waiting or standby state.
(See Fig.3 for acknowledge signal (ACK signal) response.)
Start condition (start bit)
SCL
1
(from µ-COM)
8
9
SDA
(µ-COM output data)
SDA
(IC output data)
Acknowledge signal (ACK signal)
Fig.3 Acknowledge (ACK signal) response
(during write and read slave address input)
(7) Byte write cycle
BR24C01A-W / AF-W / AFJ-W / AFV-W
S
W
T
R
A
I
R
SLAVE
T
T
ADDRESS
E
SDA
LINE
1 0 1 0 A2 A1 A0
WORD
ADDRESS
∗
WA
6
WA
0
D7
RA
A
/C
C
WK
K
WP
DATA
S
T
O
P
D0
A
C
K
Fig.4
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