ISD4002 SERIES
7.2.2. SPI Diagrams
MOSI
Input Shift Register
(Loaded to Row Counter
only if IAB = 0)
A0-A9
Row Counter
Select Logic
MISO
OVF EOM
P0-P9
Output Shift Register
FIGURE 3: SPI INTERFACE SIMPLIFIED BLOCK DIAGRAM
The following diagram describes the SPI port and the control bits associated with it.
MISO
MOSI
OVF EOM P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 X 0 0 0
LSB
MSB
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 0 C0 C1 C2 C3 C4
Message Cueing (MC)
Ignore Address Bit (IAB)
Power Up (PU)
Play/Record (P/R)
RUN
FIGURE 4: SPI PORT
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Publication Release Date: May 17, 2007
Revision 1.4