LPC8N04 데이터 시트보기 (PDF) - NXP Semiconductors.

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LPC8N04

32-bit ARM Cortex®-M0+ microcontroller; 32 kB flash and 8 kB SRAM; NFC/RFID ISO 14443 type A interf

NXP Semiconductors. 

NXP Semiconductors

LPC8N04

32-bit ARM Cortex-M0+ microcontroller

The SFRO runs at 8 MHz. The system clock is derived from it and can be set to 8 MHz,

4 MHz, 2 MHz, 1 MHz, 500 kHz, 250 kHz, 125 kHz or 62.5 kHz (Note: some features are

not available when using the lower clock speeds). The TFRO runs at 32.768 kHz and is

the clock source for the timer unit. The TFRO cannot be disabled.

Following reset, the LPC8N04 starts operating at the default 500 kHz system clock

frequency to minimize dynamic current consumption during the boot cycle.

The SYSAHBCLKCTRL register gates the system clock to the various peripherals and

memories. The temperature sensor receives a fixed clock frequency, irrespective of the

system clock divider settings, while the digital part uses the system clock (AHB clock 0).

SYSTEM FRO

(8 MHz)

SYSCLKTRIM

SYSCLKDIV[2:0]

SYSTEM CLOCK

DIVIDER

SYSAHBCLKCTRL

fixed-frequency taps

SSPCLKDIV

system clock (AHB clock 0)

peripheral clocks

analog peripheral clocks

SPI/SSP CLOCK

DIVIDER

SPI/SSP

0

WDTSEL

WATCHDOG CLOCK

DIVIDER

WDTCLKDIV

TIMER FRO

(32 kHz)

TMRCLKTRIM

0

TMRUEN

Fig 4. LPC8N04 clock generator block diagram

WDT_PCLK

PMU/always-on-domain

wake-up timer

aaa-015352

8.3.2 Reset

Reset has three sources on the LPC8N04: the RESETN pin, watchdog reset and a

software reset.

LPC8N04

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 1.3 — 15 March 2018

© NXP Semiconductors N.V. 2018. All rights reserved.

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