CXA2112R 데이터 시트보기 (PDF) - Sony Semiconductor
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CXA2112R Datasheet PDF : 23 Pages
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CXA2112R
Pin
No.
Symbol
I/O
Standard
voltage level
50 MCLK
51 MCLK/
I
PECL
differential
Equivalent circuit
VDD
Description
VDD
20k
50
1k
VDD
51
100µ
20k
1k
10µ
Dot clock input.
52 INV_CNT
I
High: ≥ 2.5V
Low: ≤ 0.8V
VDD
2k
52
VDD
10µ
Dot clock phase invert
control.
54 CLK_OUT
55 CLK_OUT/
I
VDD – 0.3V
to VDD
59 CLK_IN
61 CLK_IN/
I
VDD – 0.3V
to VDD
I
VDD VDD
54
55
1m
VDD
VDD VDD
2k
2k
145
59
100µ
VDD
145
61
Phase adjusted dot clock
output.
On-chip timing generator
clock input.
Connect directly to Pins 54
and 55.
62 PRG
I
High: ≥ 2.5V
Low: ≤ 0.8V
VDD
145
62
VDD
VDD
150k
50k
50k
Horizontal sync signal PRG
input.
Refer to Timing Chart.
–7–
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