MAX4885 데이터 시트보기 (PDF) - Maxim Integrated
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MAX4885 Datasheet PDF : 13 Pages
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Complete VGA 1:2 or 2:1 Multiplexer
standard VGA signals. The charge pump can be dis-
abled to eliminate charge-pump noise; however, RGB
switch performance is slightly degraded. Connect QP
to ground for normal operation.
Horizontal/Vertical Sync Multiplexer
1:2 Multiplexer Mode
The MAX4885 provides two modes of operation for the
HSYNC and VSYNC signals. In 1:2 mode (M = 0), the
HSYNC/VSYNC inputs are buffered to provide level shift-
ing and drive capability to meet the VESA specification.
2:1 Multiplexer Mode
In 2:1 mode (M = 1), the HSYNC/VSYNC output buffers
are disabled, and switches pass signals directly. The
HSYNC and VSYNC switches/buffers are identical, and
either input can be used to route HSYNC and
VSYNC signals.
Display Data Channel Multiplexer
The MAX4885 provides two voltage-clamped switches
to route DDC signals (see Table 3). Each switch
clamps signals to a diode drop less than the voltage
applied on VCL. Supply +3.3V on VCL to provide volt-
age clamping for VESA I2C-compatible signals. If volt-
age clamping is not required, connect VCL to V+. The
DDCA and DDCB switches are identical, and each
switch can be used to route either DDC signal.
ESD Protection
As with all Maxim devices, ESD-protection structures
are incorporated on all pins to protect against electro-
static discharges encountered during handling and
assembly. Additionally, the MAX4885 is protected to
±8kV on RGB, HSYNC, VSYNC, and DDC switches by
the Human Body Model (HBM). For optimum ESD per-
formance, bypass each V+ pin to ground with a 0.1µF
or larger ceramic capacitor.
Human Body Model (HBM)
Several ESD testing standards exist for measuring the
robustness of ESD structures. The ESD protection of
the MAX4885 is characterized with the Human Body
Model. Figure 5 shows the model used to simulate an
ESD event resulting from contact with the human body.
The model consists of a 100pF storage capacitor that is
charged to a high voltage, then discharged through a
1.5kΩ resistor. Figure 6 shows the current waveform
when the storage capacitor is discharged into a low
impedance.
ESD Test Conditions
ESD performance depends on a variety of conditions.
Please contact Maxim for a reliability report document-
ing test setup, methodology, and results.
Table 2. HV Truth Table
EN
M
SEL
FUNCTION
1:2 Mode
0
0
0
Buffers Enabled
H0 to H1
V0 to V1
1:2 Mode
0
0
1
Buffers Enabled
H0 to H2
V0 to V2
2:1 Mode
0
1
0
Buffers Disabled
H0 to H1
V0 to V1
0
1
1
X
X = Don’t Care
2:1 Mode
1
Buffers Disabled
H0 to H2
V0 to V2
X
H_, V_
High Impedance
Table 3. DDC Truth Table
EN
SEL
FUNCTION
0
0
DDCA0 to DDCA1
DDCB0 to DDCB1
0
1
DDCA0 to DDCA2
DDCB0 to DDCB2
1
X
DDCA_, DDCB_
High Impedance
X = Don’t Care
Applications Information
1:2 Multiplexer for Low-Voltage Graphics
Controllers
The MAX4885 provides the level shifting necessary to
drive two standard VGA ports from a graphics con-
troller as low as +2.2V. In 1:2 mode, internal buffers
drive the HSYNC and VSYNC signals to VGA standard
TTL levels. The DDC multiplexer provides level shifting
by clamping signals to a diode drop less than VCL (see
the Typical Operating Circuit). Connect VCL to +3.3V
for normal operation, or to V+ to disable voltage clamp-
ing for DDC signals.
10 ______________________________________________________________________________________
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