HI-8685(2001) 데이터 시트보기 (PDF) - Holt Integrated Circuits

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HI-8685
(Rev.:2001)

ARINC INTERFACE DEVICE ARINC 429 & 561 Serial Data to 16-Bit Parallel Data

Holt Integrated Circuits 

HI-8685, HI-8686

PIN DESCRIPTIONS

SIGNAL

FUNCTION

DESCRIPTION

DATA RDY OUTPUT

D0 to D15

GND

READ

PARITY ENB

OUTPUT

POWER

INPUT

INPUT

ERROR

OUTPUT

RINA/RINA-10

RINB/RINB-10

RESET

TESTA

INPUT

INPUT

INPUT

INPUT

TESTB

INPUT

GAPCLK

INPUT

Vcc

POWER

Receiver data ready flag. A high level indicates data is available in the receive

buffer. Flag goes low when the first 16-bit byte is read.

16-bit parallel data bus (tri-state)

0V

Read strobe. A low level transfers receive buffer data to the data bus

Parity Enable - A high level activates odd parity checking which replaces the

32nd ARINC bit with an error bit. Otherwise, the 32nd ARINC bit is unchanged

Error Flag. A high level indicates a bit count error (number of ARINC bits was

less than or greater than 32) and/or a parity error if parity detection was enabled

(PARITY ENB high)

Positive direct ARINC serial data input (both RINA and RINA-10 on HI-8686)

Negative direct ARINC serial data input (both RINB and RINB-10 on HI-8686)

Internal logic states are initialized with a low level

Used in conjunction with the TESTB input to bypass the built-in analog line

receiver circuitry

Used in conjunction with the TESTA input to bypass the built-in analog line

receiver circuitry

Gap Clock. Determines the minimum time required between ARINC words for

detection. The minimum word gap time is between 16 and 17 clock cycles of

this signal.

+5V ±10% supply

FUNCTIONAL DESCRIPTION

The HI-8685 and HI-8686 are serial to 16-bit parallel convert-

ers. The incoming data stream is serially shifted into an input

register, checked for errors, and then transferred in parallel to

a 32-bit receive buffer. The receive data can be accessed us-

ing two 16-bit parallel read operations while the next serial

data steam is being received.

lation, the buffered inputs drive a differential amplifier. The

differential signal is compared to levels derived from a divider

between VCC and GND. The nominal settings correspond to

a One/Zero amplitude of 6.0V and a Null amplitude of 3.3V. A

valid ARINC One/Zero input sets a latch and a Null input re-

sets the latch.

RECEIVER INPUTS

HI-8685-10 ARINC INPUTS (RINA-10 & RINB-10)

The block diagram for both the HI-8685 and HI-8685-10 prod-

ucts is found in Figure 1. Both have built-in receivers elimi-

nating the need for additional external ARINC level detection

circuitry. The only difference between the two products is the

amount of internal resistance in series with each ARINC in-

put.

Since any added external series resistance will affect the volt-

age translation, the HI-8685-10 product has only 25KΩ of

the 35KΩ series resistance required for proper ARINC 429

level detection. The remaining 10KΩ required is available to

the user for incorporation in external circuitry such as for

lightning protection.

HI-8685 ARINC INPUTS (RINA & RINB)

Typically 35KΩ resistors are in series with both the RINA and

RINB ARINC 429 inputs. They connect to level translators

whose resistance to GND is typically 10KΩ. After level trans-

HI-8686 ARINC INPUTS

The HI-8686 has both sets of ARINC inputs, RINA/RINA-10

and RINB/RINB-10 available to the user.

HOLT INTEGRATED CIRCUITS

2

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