GS881E18T 데이터 시트보기 (PDF) - Giga Semiconductor
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GS881E18T Datasheet PDF : 34 Pages
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Preliminary
GS881E18/36T-11/11.5/100/80/66
Mode Pin Functions
Mode Name
Pin Name State
Function
Burst Order Control
LBO
L
H or NC
Linear Burst
Interleaved Burst
Output Register Control
FT
L
H or NC
Flow Through
Pipeline
Power Down Control
ByteSafe Data Parity Control
L or NC
ZZ
H
DP
L
H or NC
Active
Standby, IDD = ISB
Check for Odd Parity
Check for Even Parity
Note:
There are pull-up devices on the LBO, DP and FT pins and a pull down device on the ZZ pin, so those input pins can be unconnected and the
chip will operate in the default states as specified in the above table.
Burst Counter Sequences
Linear Burst Sequence
A[1:0] A[1:0] A[1:0] A[1:0]
1st address
00
01
10
11
2nd address
01
10
11
00
3rd address
10
11
00
01
4th address
11
00
01
10
Note: The burst counter wraps to initial state on the 5th clock.
Interleaved Burst Sequence
A[1:0] A[1:0] A[1:0] A[1:0]
1st address
00
01
10
11
2nd address
01
00
11
10
3rd address
10
11
00
01
4th address
11
10
01
00
Note: The burst counter wraps to initial state on the 5th clock.
BPR 1999.05.18
Rev: 1.10 9/2000
8/34
© 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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