MK10FX1M0ACMC15 데이터 시트보기 (PDF) - NXP Semiconductors.

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MK10FX1M0ACMC15

K10 Sub-Family

NXP Semiconductors. 

Peripheral operating requirements and behaviors

Table 15. MCG specifications (continued)

Symbol Description

Min.

FLL

ffll_ref

fdco

FLL reference frequency range

DCO output

frequency range

Low range (DRS=00)

640 × ffll_ref

Mid range (DRS=01)

31.25

20

40

1280 × ffll_ref

Mid-high range (DRS=10)

60

1920 × ffll_ref

High range (DRS=11)

80

fdco_t_DMX32 DCO output

frequency

2560 × ffll_ref

Low range (DRS=00)

—

732 × ffll_ref

Mid range (DRS=01)

—

1464 × ffll_ref

Mid-high range (DRS=10)

—

2197 × ffll_ref

High range (DRS=11)

—

Jcyc_fll

tfll_acquire

FLL period jitter

2929 × ffll_ref

• fDCO = 48 MHz

• fDCO = 98 MHz

FLL target frequency acquisition time

—

—

—

PLL

fvco

VCO operating frequency

Ipll

PLL operating current

• PLL @ 96 MHz (fosc_hi_1 = 8 MHz, fpll_ref =

2 MHz, VDIV multiplier = 48)

48.0

—

Ipll

PLL operating current

• PLL @ 48 MHz (fosc_hi_1 = 8 MHz, fpll_ref =

—

2 MHz, VDIV multiplier = 24)

fpll_ref PLL reference frequency range

2.0

Jcyc_pll PLL period jitter (RMS)

• fvco = 48 MHz

—

• fvco = 100 MHz

—

Typ.

Max.

Unit

—

20.97

39.0625

25

kHz

MHz

41.94

50

MHz

62.91

75

MHz

83.89

100

MHz

23.99

—

MHz

47.97

—

MHz

71.99

—

MHz

95.98

—

MHz

180

—

ps

150

—

—

1

ms

—

100

MHz

1060

—

µA

600

—

µA

—

4.0

MHz

120

—

ps

50

—

ps

Notes

2, 3

4, 5

6

7

7

8

Jacc_pll

PLL accumulated jitter over 1µs (RMS)

• fvco = 48 MHz

• fvco = 100 MHz

8

—

1350

—

ps

—

600

—

ps

Dlock

Dunl

Lock entry frequency tolerance

Lock exit frequency tolerance

± 1.49

—

± 2.98

%

± 4.47

—

± 5.97

%

Table continues on the next page...

K10 Sub-Family Data Sheet, Rev. 3, 6/2013.

Freescale Semiconductor, Inc.

27

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