NCP1612B 데이터 시트보기 (PDF) - ON Semiconductor

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NCP1612B

Enhanced, High‐Efficiency Power Factor Controller

ON Semiconductor 

NCP1612A, NCP1612B, NCP1612A1, NCP1612A2, NCP1612A3, NCP1612B2

Current Information Generation

The “FFcontrol” pin sources a current that is

representative of the input current. In practice, Ipin5 is built

by multiplying the internal control signal (VREGUL, i.e., the

internal signal that controls the on-time) by the sense voltage

(pin 4) that is proportional to the input voltage. The

multiplier gain (Km of Figure 63) is three times less in

high-line conditions (that is when the “LLine” signal from

the brown-out block is in low state) so that Ipin5 provides a

voltage representative of the input current across resistor

RFF placed between pin 5 and ground. Pin 5 voltage is the

current information.

VSENSBEOPipnin

IREGUL

IBO

V to I

IBO

converter

VCONTRVOcLonPtirnol pin

Multiplier

LLine

FFFCFOcNoTnRtOroLlPpiinn

RFF

V to I

converter

IREGUL

IREGUL = K • VREGUL

Km • IREGUL • IBO

SSUUMM

+

RRAAMMPP

VSKIP_H / VSKIP1_VL

pfpcfOcKOK

SsKkiIpP2

Figure 63. Generation of the Current Information

Skip Mode

As illustrated in Figure 63, the circuit also skips cycles

near the line zero crossing where the current is very low.

A comparator monitors the pin 5 voltage (“FFcontrol”

voltage) and inhibits the switching operation when Vpin5 is

lower than VSKIP_L (0.90 V typically for the NCP1612A3,

0.65 V for the other versions). Switching resumes when

Vpin5 exceeds VSKIP_H (1 V typically for the NCP1612A3,

0.75 V for the other versions). This function prevents circuit

operation when the power transfer is particularly inefficient

at the expense of slightly increased current distortion. When

superior power factor is needed, this function can be

inhibited offsetting the “FFcontrol” pin by a voltage higher

than VSKIP_H. The skip mode capability is disabled

whenever the PFC stage is not in nominal operation (as

dictated by the “pfcOK” signal − see block diagram and

“pfcOK Internal Signal” Section).

The circuit does not abruptly interrupt the switching when

Vpin5 goes below VSKIP_L. Instead, the signal VTON that

controls the on-time is gradually decreased by grounding the

VREGUL signal applied to the VTON processing block (see

Figure 68). Doing so, the on-time smoothly decays to zero

in 3 to 4 switching periods typically. Figure 64 shows the

practical implementation.

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