MAX11055(2011) 데이터 시트보기 (PDF) - Maxim Integrated
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MAX11055 Datasheet PDF : 27 Pages
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MAX11044/MAX11045/MAX11046/
MAX11054/MAX11055/MAX11056
4-/6-/8-Channel, 16-/14-Bit,
Simultaneous-Sampling ADCs
RS
=
VFAULT_MAX
20mA
- 7V
where VFAULT_MAX is the maximum voltage that the
source produces during a fault condition.
Figures 2 and 3 illustrate the clamp circuit voltage-cur-
rent characteristics for a source impedance RS =
1280Ω. While the input voltage is within the ±(VAVDD +
300mV) range, no current flows in the input clamps.
Once the input voltage goes beyond this voltage range,
the clamps turn on and limit the voltage at the input pin.
Applications Information
Digital Interface
The bidirectional, parallel, digital interface, CR0–CR3,
sets the 4-bit configuration register. This interface con-
figures the following control signals: chip select (CS),
read (RD), write (WR), end of conversion (EOC), and
convert start (CONVST). Figures 6 and 7 and the
Timing Characteristics in the Electrical Characteristics
table show the operation of the interface.
DB0–DB15/DB13 output the 16-/14-bit conversion result.
All bits are high impedance when RD = 1 or CS = 1.
CR3 (Int/Ext Reference)
CR3 selects the internal or external reference. The POR
default = 0.
0 = internal reference, REFIO internally driven through a
10kΩ resistor, bypass with 0.1µF capacitor to AGND.
1 = external reference, drive REFIO with a high-quality
reference.
CR2 (Output Data Format)
CR2 selects the output data format. The POR default = 0.
0 = offset binary.
1 = two’s complement.
CR1 must be set to 0.
CR1 (Reserved)
CR0 (CONVST Mode)
CR0 selects the acquisition mode. The POR default = 0.
0 = CONVST controls the acquisition and conversion.
Drive CONVST low to start acquisition. The rising edge
of CONVST begins the conversion.
1 = acquisition mode starts as soon as the previous
conversion is complete. The rising edge of CONVST
begins the conversion.
Programming the Configuration Register
To program the configuration register, bring the CS and
WR low and apply the required configuration data on
CR3–CR0 of the bus and then raise WR once to save
changes.
CAUTION: When the configuration register is not
being programmed, the host driving CR3–CR0 must
relinquish the bus when the conversion results of
the ADC are being read!
Table 1. Configuration Register
CR3
CR2
CR1
Int/Ext
Reference
Output
Must be set
Data Format
to 0
CR0
CONVST
Mode
30
RS = 1280Ω
20 VAVDD = 5V
AT CH_ INPUT
10
0
AT SOURCE
-10
-20
-30
-50 -30 -10 10
30
50
SIGNAL VOLTAGE AT SOURCE AND PIN (V)
Figure 2. Input Clamp Characteristics
30
RS = 1280Ω
20 VAVDD = 5V
10
AT SOURCE
0
AT CH_ INPUT
-10
-20
-30
-8 -6 -4 -2 0 2 4 6 8
SIGNAL VOLTAGE AT SOURCE AND PIN (V)
Figure 3. Input Clamp Characteristics (Zoom In)
Maxim Integrated
17
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