SY100S321(1999) 데이터 시트보기 (PDF) - Micrel
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SY100S321 Datasheet PDF : 5 Pages
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LOW-POWER 9-BIT
INVERTER
SY100S321
FEATURES
DESCRIPTION
s Max. propagation delay of 700ps
s IEE min. of –55mA
s Extended supply voltage option:
VEE = –4.2V to –5.5V
s Voltage and temperature compensation for
improved noise immunity
s 70% faster than Fairchild 300K at lower power
s Internal 75KΩ input pull-down resistors
s Function and pinout compatible with Fairchild F100K
s Available in 24-pin CERPACK and 28-pin PLCC
packages
BLOCK DIAGRAM
The SY100S321 is a monolithic 9-bit inverter. The device
contains nine inverting buffer gates with single input and
output.
PIN CONFIGURATIONS
D6
D7
VEE
VEES
VCCA
D8
D9
11 10 9 8 7 6 5
12
4
13
3
14
Top View
2
15
PLCC
J28-1
1
16
28
17
27
18
26
19 20 21 22 23 24 25
O7
O8
VCCA
VCC
VCC
O9
O1
D1
O1
D2
O2
D3
O3
D4
O4
D5
O5
D6
O6
D1
D2
D3
VCCA
O3
O2
24 23 22 21 20 19
1
18
2
17
3
Top View 16
4
Flatpack
F24-1
15
5
14
6
13
7 8 9 10 11 12
D5
D4
VCCA
Q4
Q5
Q6
D7
O7
D8
O8
D9
O9
PIN NAMES
Pin
D1 – D9
Q1 – Q9
VEES
VCCA
Function
Data Inputs
Data Outputs
VEE Substrate
VCCO for ECL Outputs
Rev.: G Amendment: /0
1
Issue Date: July, 1999
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