78Q8430 데이터 시트보기 (PDF) - Teridian Semiconductor Corporation

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78Q8430

10/100 Ethernet MAC and PHY

Teridian Semiconductor Corporation 

78Q8430 Data Sheet

DS_8430_001

3.2.8 Mode Pins

Table 9: Chip Mode Pin Descriptions

Signal

Pin Number Type Description

BUSMODE

83

CLKMODE

85

WAITMODE

84

I BUSMODE, CLKMODE, WAITMODE Configuration

I 0,0,0 = Sync bus, ext. system clock, memwait act low

I 0,0,1 = Sync bus, ext. system clock, memwait act high

0,1,0 = Reserved

0,1,1 = Reserved

1,0,0 = Async bus, ext. system clock, memwait act low

1,0,1 = Async bus, ext. system clock, memwait act high

1,1,0 = Async bus, int. system clock, memwait act low

1,1,1 = Async bus, int. system clock, memwait act high

ENDIAN0

79

I Data Bus Endian Select

ENDIAN1

80

I 0,0 = Big endian (MSB at high bit positions)

0,1 = Bytes are little endian inside 16-bit words

1,0 = Word endian (MSW at low bit positions)

1,1 = Little endian (MSB at low bit positions)

BOOTSZ1

100

I GBI Bus Size

BOOTSZ0

1

I BOOTSZ[1:0]: is strapped to indicate the GBI bus size:

00 = Bus is 32 bits wide

01 = Bus is 16 bits wide. Only DATA[15:0] are used.

10 = Bus is 8 bits wide. Only DATA[7:0] are used.

11 = Reserved

Notes:

1. The internal PHY should never be powered down when the internal system clock is selected by

the CLKMODE pin (CLKMODE=1)

2. There is no external visibility for the system clock when the internal clock mode is selected. The

GBI interface must therefore always be used in asynchronous bus mode.

3.2.9 JTAG Pins

Signal

TRST

TCLK

TMS

Pin Number

5

6

3

TDI

4

TDO

81

Table 10: JTAG Pin Descriptions

Type

I

I

IU

IU

O

Description

Test Reset (active low)

System provided reset for JTAG logic.

Test Clock

System provided clock for JTAG logic.

Test Mode Select

Enables JTAG boundary scan using serial in/serial out ports.

Sampled on rising edge of TCLK.

Test Data In

Serial input port for clocking in test data to be shifted to the

output at the end of the boundary scan chain (TDO).

Test Data Out

Serial output port for clocking out test data shifted from the

input at the beginning of the boundary scan chain (TDI).

16

Rev. 1.2

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