MAXQ3120 데이터 시트보기 (PDF) - Maxim Integrated

부품명

상세내역

제조사

MAXQ3120

High-Precision ADC Mixed-Signal Microcontroller

Maxim Integrated 

High-Precision ADC

Mixed-Signal Microcontroller

Detailed Description

The following is an introduction to the primary features

of the microcontroller. More detailed descriptions of the

device features can be found in the data sheets, errata

sheets, and user’s guides described later in the

Additional Documentation section.

MAXQ Core Architecture

The MAXQ3120 is a low-cost, high-performance,

CMOS, 16-bit RISC microcontroller with flash memory

and an integrated 112-segment LCD controller. It is

structured on a highly advanced, accumulator-based,

16-bit RISC architecture. Fetch and execution opera-

tions are completed in one cycle without pipelining,

because the instruction contains both the op code and

data. The result is a streamlined 8 million instructions-

per-second (MIPS) microcontroller.

The highly efficient core is supported by a 16-level

hardware stack, enabling fast subroutine calling and

task switching. Data can be quickly and efficiently

manipulated with three internal data pointers. Multiple

data pointers allow more than one function to access

data memory without having to save and restore data

pointers each time. The data pointers can automatically

increment or decrement following an operation, elimi-

nating the need for software intervention. As a result,

the application speed is greatly increased.

Instruction Set

The instruction set is composed of fixed-length, 16-bit

instructions that operate on registers and memory loca-

tions. The instruction set is highly orthogonal, allowing

arithmetic and logical operations to use any register

along with the accumulator. System registers control

functionality common to all MAXQ microcontrollers,

while peripheral registers control peripherals and func-

tions specific to the MAXQ3120. All registers are subdi-

vided into register modules. The family architecture is

modular, so that new devices and modules can reuse

code developed for existing products.

The architecture is transport-triggered. This means that

writes or reads from certain register locations can also

cause side effects to occur. These side effects form the

basis for the higher-level op codes defined by the

assembler, such as ADDC, OR, JUMP, etc. The op

codes are actually implemented as MOVE instructions

between certain system register locations, while the

assembler handles the encoding, which need not be a

concern to the programmer.

The 16-bit instruction word is designed for efficient exe-

cution. Bit 15 indicates the format for the source field of

the instruction. Bits 0 to 7 of the instruction represent the

source for the transfer. Depending on the value of the

format field, this can either be an 8-bit immediate value

or a source register. If this field represents a register, the

lower four bits contain the module specifier and the

upper four bits contain the register index in that module.

Bits 8 to 14 represent the destination for the transfer.

This value always represents a destination register, with

the lower four bits containing the module specifier and

the upper three bits containing the register subindex

within that module.

The following types of instructions require the use of

the prefix register, PFX, to supply additional data.

• Loading a 16-bit immediate value (with a nonzero

high byte) into any register

• Branching to a 16-bit absolute destination address

(LJMP or LCALL)

• Selecting one of the upper 8 registers in a system

register module as a destination

• Selecting one of the upper 16 registers in a periph-

eral register module as a source

• Selecting one of the upper 24 registers in a periph-

eral register module as a destination

For any of these instruction types, the prefix register is

used to supply the additional immediate value bits,

source bits, and destination bits as needed. This prefix

register write is inserted automatically by the assembler

and requires only one additional execution cycle for

any or all of these conditions.

Memory Organization

The device incorporates several memory areas:

• 2kWords utility ROM

• 16kWords of flash memory for program storage

• 256 words of SRAM for storage of temporary vari-

ables

• 16-level, 16-bit-wide stack memory for storage of

program return addresses and general-purpose use

The memory is arranged by default in a Harvard archi-

tecture, with separate address spaces for program and

data memory. The configuration of program and data

space depends on the current execution location.

• When executing code from flash memory, the SRAM

and utility ROM are accessible in data space.

• When executing code from SRAM, the flash memory

and utility ROM are accessible in data space.

• When executing code from the utility ROM, the flash

memory and SRAM are accessible in data space.

10 ____________________________________________________________________

Share Link: