M34D64-W 데이터 시트보기 (PDF) - STMicroelectronics

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M34D64-W

64 Kbit serial I²C bus EEPROM with hardware write control on top quarter of memory

STMicroelectronics 

M34D64-W

Device operation

3.7

Byte Write

After the Device Select code and the address bytes, the bus master sends one data byte. If

the addressed location is Write-protected (top quarter of the memory), by Write Control

(WC) being driven high, the location is not modified. The bus master terminates the transfer

by generating a Stop condition, as shown in Figure 7.: Write mode sequences with WC = 0

(data write enabled).

3.8

Page Write

The Page Write mode allows up to 32 bytes to be written in a single Write cycle, provided

that they are all located in the same ’row’ in the memory: that is, the most significant

memory address bits (b12-b5) are the same. If more bytes are sent than will fit up to the end

of the row, a condition known as ‘roll-over’ occurs. This should be avoided, as data starts to

become overwritten in an implementation dependent way.

The bus master sends from 1 to 32 bytes of data. If Write Control (WC) is high, the contents

of the addressed top quarter of the memory location are not modified. After each byte is

transferred, the internal byte address counter (the 5 least significant address bits only) is

incremented. The transfer is terminated by the bus master generating a Stop condition.

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