DS3254 데이터 시트보기 (PDF) - Maxim Integrated
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DS3254 Datasheet PDF : 71 Pages
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DS3251/DS3252/DS3253/DS3254
FEATURES (CONTINUED)
Receiver
AGC/equalizer block handles from 0 to 15dB of cable loss
Loss-of-lock (LOL) PLL status indication
Interfaces directly to a DSX monitor signal (~20dB flat loss) using built-in preamp
Digital and analog loss-of-signal (LOS) detectors (ANSI T1.231 and ITU G.775)
Optional B3ZS/HDB3 decoder
Line-code violation output pin and counter
Binary or bipolar framer interface
On-board 215 - 1 and 223 - 1 PRBS detector
Clock inversion for glueless interfacing
Tri-state clock and data outputs support protection switching applications
Per-channel power-down control
Transmitter
Binary or bipolar framer interface
Gapped clock capable up to 51.84MHz
Wide 50 ± 20% transmit clock duty cycle
Clock inversion for glueless interfacing
Optional B3ZS/HDB3 encoder
On-board 215 - 1 and 223 - 1 PRBS generator
Complete DS3 AIS generator (ANSI T1.107)
Unframed all-ones generator (E3 AIS)
Line build-out (LBO) control
Tri-state line driver outputs support protection switching applications
Per-channel power-down control
Output driver monitor
Jitter Attenuator
On-chip crystal-less jitter attenuator
Meets all applicable ANSI, ITU, ETSI and Telcordia jitter transfer and output jitter requirements
Can be placed in the transmit path, receive path or disabled
Selectable FIFO depth: 16, 32, 64 or 128 bits
Overflow and underflow status indications
Clock Adapter
Operates from a single DS3, E3, STS-1, 19.44 MHz, 38.88 MHz, or 77.76 MHz master clock
Synthesizes clock rates that are not provided externally
Use of common system timing frequencies such as 19.44 MHz eliminates the need for any local oscillators,
reduces cost and board space
Very small jitter gain and intrinsic jitter generation
Optionally provides synthesized clocks on output pins for use by neighboring components, such as framers or
mappers
Parallel CPU Interface
Multiplexed or nonmultiplexed 8-bit interface
Configurable for Intel mode (CS, WR, RD) or Motorola mode (CS, DS, R/W)
SPI CPU Interface
Operation up to 10 Mbit/s
Burst mode for multi-byte read and write accesses
Programmable clock polarity and phase
Half-duplex operation gives option to tie SDI and SDO together externally to reduce wire count
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