DS3254 데이터 시트보기 (PDF) - Maxim Integrated

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DS3254

Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs

Maxim Integrated 

4. BLOCK DIAGRAMS

Figure 4-1. CPU Bus Mode Block Diagram

T3MCLK E3MCLK STMCLK

VDD

VSS

Power

Supply

Clock

Adapter

TCLKn

master clock

RXPn

RXNn

TDMn

Analog

Local

Loopback

Automatic

Gain

Control

+

Adaptive

Equalizer

Clock &

Data

Recovery

ALOS

squelch

Driver

Monitor

TXPn

TXNn

Loopback Control

TTSn

RLOSn

Digital LOS

Detector

B3ZS/HDB3

Decoder

Remote

Loopback

Digital

Local

Loopback

B3ZS/

HDB3

Encoder

PARALLEL INTERFACE

CPU Bus

Interface

and

Global

Configuration

HIZ

RST

HW = 0

MOT

ALE

CS

WR / R/W

RD / DS

A[5:0]

D[7:0]

INT

SPI INTERFACE

CPU Bus

Interface

and

Global

Configuration

HIZ

RST

HW = 0

CS

SCLK

SDI

SDO

CPHA

CPOL

INT

MOT = 0, WR = 0, RD = 0, ALE = 1

DS3251/DS3252/DS3253/DS3254

PRBS

Detector

PRBSn

Output

Drivers,

Clock

Invert

RTSn

RPOSn/RDATn

RNEGn/RLCVn

RCLKn

CPU Bus

Interface

and

Global

Configuration

Clock

Invert

AIS, 100100…,

PRBS Pattern

Generation

CPU Bus I/O

(see detailed

views below)

TPOSn/TDATn

TNEGn

TCLKn

Dallas

Semiconductor

DS325x

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