26102AVZ 데이터 시트보기 (PDF) - Renesas Electronics

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26102AVZ

Low-Noise 24-bit Delta Sigma ADC

Renesas Electronics 

ISL26102, ISL26104

Package Outline Drawing

M28.173

28 LEAD THIN SHRINK SMALL OUTLINE PACKAGE (TSSOP)

Rev 1, 5/10

A

13

9.70± 0.10

28

15

6.40

4.40 ± 0.10

2

3

PIN #1

I.D. MARK

SEE DETAIL "X"

0.20 C B A 1

H

C

SEATING PLANE

0.10 C

14

0.65

B

TOP VIEW

0.15 +0.05

-0.06

END VIEW

- 0.05

SIDE VIEW

1.20 MAX

0.90 +0.15

-0.10

0.25+-00..0065

5

0.10 M C B A

0.05 MIN

0.15 MAX

1.00 REF

GAUGE

PLANE

0.25

0°-8°

0.60 ±0.15

DETAIL "X"

(5.65)

(1.45)

NOTES:

(0.65 TYP)

(0.35 TYP)

TYPICAL RECOMMENDED LAND PATTERN

1. Dimension does not include mold flash, protrusions or gate burrs.

Mold flash, protrusions or gate burrs shall not exceed 0.15 per side.

2. Dimension does not include interlead flash or protrusion. Interlead

flash or protrusion shall not exceed 0.25 per side.

3. Dimensions are measured at datum plane H.

4. Dimensioning and tolerancing per ASME Y14.5M-1994.

5. Dimension does not include dambar protrusion. Allowable protrusion

shall be 0.08mm total in excess of dimension at maximum material

condition. Minimum space between protrusion and adjacent lead

is 0.07mm.

6. Dimension in ( ) are for reference only.

7. Conforms to JEDEC MO-153.

FN7608 Rev 0.00

October 12, 2012

Page 21 of 21

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