ISL85033 데이터 시트보기 (PDF) - Renesas Electronics

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ISL85033

Wide VIN Dual Standard Buck Regulator With 3A/3A Continuous Output Current

Renesas Electronics 

ISL85033

Pin Configuration

ISL85033

(28 LD TQFN)

TOP VIEW

28 27 26 25 24 23 22

COMP1 1

FB1 2

SS1 3

PGND1 4

BOOT1 5

PHASE1 6

PHASE1 7

21 COMP2

20 FB2

19 SS2

PD

18 PGND2

17 BOOT2

16 PHASE2

15 PHASE2

8 9 10 11 12 13 14

Pin Descriptions

PIN NUMBER

1, 21

2, 20

3, 19

4, 18

5, 17

6, 7, 15, 16

8, 9, 13, 14

10, 12

11

SYMBOL

COMP1, COMP2

FB1, FB2

SS1, SS2

PGND1, PGND2

BOOT1, BOOT2

PHASE1, PHASE2

VIN1, VIN2

EN1, EN2

VCC

PIN DESCRIPTION

COMP1, COMP2 are the output of the error amplifier.

Feedback pin for the regulator. FB is the negative input to the voltage loop error amplifier. COMP is the

output of the error amplifier. The output voltage is set by an external resistor divider connected to FB.

In addition, the PWM regulator’s power-good and undervoltage protection circuits use FB1, FB2 to monitor

the regulator output voltage.

Soft-start pins for each controller. The SS1, SS2 pins control the soft-start and sequence of their respective

outputs. A single capacitor from the SS pin to ground determines the output ramp rate. See the “Output

Tracking and Sequencing” on page 16 for soft-start and output tracking/sequencing details. If SS pins are

tied to VCC, an internal soft-start of 2ms will be used. Maximum CSS value is 100nF.

Power ground connections. Connect directly to the system GND plane.

Floating bootstrap supply pin for the power MOSFET gate driver. The bootstrap capacitor provides the

necessary charge to turn on the internal N-Channel MOSFET. Connect an external capacitor from this pin to

PHASE.

Switch node output. It connects the source of the internal power MOSFET with the external output inductor

and with the cathode of the external diode.

The input supply for the power stage of the PWM regulator and the source for the internal linear regulator

that provides bias for the IC. Place a minimum of 10µF ceramic capacitance from each VIN to GND and

close to the IC for decoupling.

PWM controller’s enable inputs. The PWM controllers are held off when the pin is pulled to ground. When

the voltage on this pin rises above 2V, the PWM controller is enabled. If EN1, EN2 pins are driven by an

external signal, the minimum off-time for EN1, EN2 should be:

EN_T_off s = 10s  CSS  2.2nF

where CSS is the soft-start pin capacitor (nF). The ISL85033 does not have debouncing to EN1, EN2 external

signals.

Output of the internal 5V linear regulator. Decouple to PGND with a minimum of 4.7µF ceramic capacitor.

This pin is provided only for internal bias of ISL85033 (not to be loaded with current over 10mA).

FN6676 Rev 8.00

February 17, 2015

Page 3 of 26

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