ISL90842 데이터 시트보기 (PDF) - Renesas Electronics

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ISL90842

Quad Digitally Controlled Variable Resistors Low Noise, Low Power I2C Bus, 256 Taps

Renesas Electronics 

ISL90842

Functional Diagram

VCC

RH0

RH1

RH2

RH3

SCL

SDA

A0

A1

Block Diagram

I2C

INTERFACE

GND

RL

RL

RL

RW0

RW1

RL

RW2

RW3

VCC

SDA

SCL

A1

A0

I2C INTERFACE

POWER-UP,

INTERFACE,

CONTROL

AND STATUS

LOGIC

WR3

WR2

WR1

WR0

DCP3

DCP2

DCP1

DCP0

RH3

RW3

*

RH2

RW2

*

RH1

RW1

*

RH0

RW0

*

Pin Descriptions

TSSOP PIN

1

2

3

4

5

6

7

8

9

10

11

12

13

14

GND

* THE RL PINS OF EACH DCP ARE LEFT FLOATING

SYMBOL

RH3

RW3

SCL

SDA

GND

RW2

RH2

RW1

RH1

A0

A1

VCC

RH0

RW0

DESCRIPTION

“High” terminal of DCP3

“Wiper” terminal of DCP3

I2C interface clock

Serial data I/O for the I2C interface

Device ground pin

“Wiper” terminal of DCP2

“High” terminal of DCP2

“Wiper” terminal of DCP1

“High” terminal of DCP1

Device address for the I2C interface

Device address for the I2C interface

Power supply pin

“High” terminal of DCP0

“Wiper” terminal of DCP0

FN8096 Rev 1.00

January 16, 2006

Page 2 of 10

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