ADM1185ARMZ 데이터 시트보기 (PDF) - Analog Devices

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ADM1185ARMZ

Quad Voltage Monitor and Sequencer

Analog Devices 

Preliminary Technical Data

ADM1185

PIN CONFIGURATIONS

GND 1

VIN1 2

VIN2 3

ADM1185

TOP VIEW

10 Vcc

9 OUT1

8 OUT2

VIN3 4 (NOT TO SCALE) 7 OUT3

VIN4 5

6 PWRGD

Figure 3. Pin Configurations

PIN FUNCTIONAL DESCRIPTIONS

Table 3.

Pin No. Name

Description

1

GND

Chip Ground Pin.

2

VIN1

Non-inverting input of comparator 1. The voltage on this pin is compared with a 0.6V reference. Can be used

to monitor a voltage rail via a resistor divider.

3

VIN2

Non-inverting input of comparator 2. The voltage on this pin is compared with a 0.6V reference. Can be used

to monitor a voltage rail via a resistor divider.

4

VIN3

Non-inverting input of comparator 3. The voltage on this pin is compared with a 0.6V reference. Can be used

to monitor a voltage rail via a resistor divider.

5

VIN4

Non-inverting input of comparator 4. The voltage on this pin is compared with a 0.6V reference. Can be used

to monitor a voltage rail via a resistor divider.

6

PWRGD

Open-drain output. During a power-up sequence (before PWRGD asserts) this output will assert high when

the voltage on VIN4 is greater than 0.6V. A time delay of 190ms (typical) is included before assertion of this

pin. After power-up (after PWRGD asserts) this output will be driven low if any of the voltages on the VIN1-

VIN4 pins falls below 0.6V.

7

OUT3

Open-drain output. During a power-up sequence (before PWRGD asserts) this output will assert high when

the voltage on VIN3 is greater than 0.6V. After power-up (after PWRGD asserts) this output will be driven low

if the voltage on VIN1 falls below 0.6V.

8

OUT2

Open-drain output. During a power-up sequence (before PWRGD asserts) this output will assert high when

the voltage on VIN2 is greater than 0.6V. After power-up (after PWRGD asserts) this output will be driven low

if the voltage on VIN1 falls below 0.6V.

9

OUT1

Open-drain output. During a power-up sequence (before PWRGD asserts) this output will assert high when

the voltage on VIN1 is greater than 0.6V. A time delay of 190ms (typical) is included before assertion of this

pin. After power-up (after PWRGD asserts) this output will be driven low if the voltage on VIN1 falls below

0.6V.

10

VCC

Positive supply input pin. The operating supply voltage range is 2.7 V to 5.5 V.

Rev. PrK | Page 5 of 12

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