LC72136 데이터 시트보기 (PDF) - SANYO -> Panasonic

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LC72136

PLL Frequency Synthesizer for Electronic Tuning

SANYO -> Panasonic 

LC72136, 72136M

Continued from preceding page.

No.

Control block/data

IF counter control data

(11) IFS

LSI test data

TEST 0 to 3

(12)

Description

• This data should be set to 1 in normal operation. Setting this data to 0 switches

the LC72136 to a reduced input sensitivity mode in which the sensitivity is reduced by

10 to 30 mVrms.

* See the “IF Counter Operation” item for details.

• LSI test data

TEST0

TEST1 All three bits must be set to 0.

TEST2

All the test data is set to 0 following a power-on reset.

DO Output Data (Serial Data Output) Structure

3. OUT mode

Related data

DO Output Data

No.

Control block/data

I/O port data

(1) I2, I1

PLL unlock data

(2) UL

IF counter binary data

(3) C19 to C0

Description

• Data latched from the states of the I/O ports, pins IO1 and IO2.

(This data reflects the pin states, regardless of whether they are in input or output mode.)

I1 ← IO1 pin state High: 1

I2 ← IO2 pin state Low: 0

• Data latched from the state of the unlock detection circuit

UL ← 0: Unlocked

UL ← 1: Locked or in detection stopped mode

• Data latched from the state of the IF counter, which is a 20-bit binary counter.

C19 ← Binary counter MSB

C0 ← Binary counter LSB

Related data

IOC1,

IOC2

UL0,

UL1

CTE,

GT0,

GT1

No. 5038-12/23

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