LC72136 데이터 시트보기 (PDF) - SANYO -> Panasonic

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LC72136

PLL Frequency Synthesizer for Electronic Tuning

SANYO -> Panasonic 

LC72136, 72136M

When directly outputting data from the DO pin (set up by the DO pin control data)

Since the DO pin outputs the unlocked state (locked: high, unlocked: low) the timing considerations in the technique

described in the previous section are not necessary. After changing the value of N, the locked state can be determined

after waiting at least two periods of the reference frequency.

Notes on Clock Time Base Usage

When the clock time base output is used, the value of the pull-up resistor for the output pin (BO1) must be at least 100 kΩ.

This is to avoid degradation of the VCO C/N characteristics when using the built-in low-pass filter transistor to form the

loop filter. Since the clock time base output pin and the low-pass filter transistor ground are the same node in the IC, the

time base output pin current fluctuations must be suppressed to limit the influence on the low-pass filter. We recommend

the use of a Schmitt input on the receiving controller (microprocessor) to prevent chattering.

Other Items

1. Notes on the Phase Comparator Dead Zone

DZ1

DZ0 Dead-zone mode

0

0

DZA

0

1

DZB

1

0

DZC

1

1

DZD

Charge pump

ON/ON

ON/ON

OFF/OFF

OFF/OFF

Dead zone

– –0 sec

–0 sec

+0 sec

+ +0 sec

Since correction pulses are output from the charge pump even if the PLL is locked when the charge pump is in the

ON/ON state, the loop can easily become unstable. This point requires special care when designing application

circuits.

The following problems may occur in the ON/ON state.

• Side band generation due to reference frequency leakage

• Side band generation due to both the correction pulse envelope and low frequency leakage

No. 5038-20/23

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