674R-01ILFT 데이터 시트보기 (PDF) - Integrated Device Technology
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674R-01ILFT Datasheet PDF : 8 Pages
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ICS674-01
USER CONFIGURABLE DIVIDER
CLOCK DIVIDER
Parameter
Short Circuit Current
On-Chip Pull-up Resistor
Input Capacitance
Symbol
Conditions
IOS Each output
RPU A, B, S select pins
CIN A, B, S select pins
Min.
Typ.
±70
270
5
Max.
Units
mA
kΩ
pF
AC Electrical Characteristics
VDD = 5 V, Ambient Temperature -40 to +85° C, CLOAD at CLK = 15 pF, unless stated otherwise
Parameter
Symbol
Conditions
Min. Typ. Max. Units
Input Frequency, Divider A
Input Frequency, Divider B
fIN
3.3 V
3.3 V
0
135 MHz
0
180 MHz
Input Frequency, Divider A
5V
0
200 MHz
Input Frequency, Divider B
5V
0
235 MHz
Input Frequency, Divider A
(Industrial temperature)
fIN at 3.3 V, +85° C
0
125 MHz
Input Frequency, Divider B
(Industrial temperature)
at 3.3 V, +85° C
0
170 MHz
Input Frequency, Divider A
(Industrial temperature)
at 5 V, +85° C
0
190 MHz
Input Frequency, Divider B
(Industrial temperature)
at 5 V, +85° C
0
220 MHz
Output Rise Time
Output Fall Time
OUTB Clock Duty Cycle1
OUTB Clock Duty Cycle
odd post dividers
OUTA Clock Duty Cycle1
tOR 20% to 80%
tOF 80% to 20%
tDC at VDD/2
at VDD/2, except PD=1
at VDD/2
1.5
ns
1.5
ns
45 49 to 51 55 %
40
60 %
20
98.5 %
Peak-to-Peak Jitter
15 pF
400 ps
Cycle-to-Cycle Jitter
30 pF loads
300 ps
Propagation Delay,
Divider A
TPA VDD = 3.3 V, +25° C
VDD = 5.0 V, +25° C
6.5
ns
4.5
ns
Propagation Delay,
Divider B + Post Divider
TPB VDD = 3.3 V, +25° C
VDD = 5.0 V, +25° C
20
ns
13
ns
1 The duty cycle of OUTA is dependent on the selected divide. This because OUTA goes low for 1 input clock
cycles on INA. For example, if a divide of 20 is selected, the duty cycle will be 90%. Simlarly, if PD=1 is selected for
OUTB, the duty cycle will be dependent on the selected divide. In this case, OUTB goes high for approximately 8
input clock cycles on INB.
IDT™ / ICS™ USER CONFIGURABLE DIVIDER
6
ICS674-01 REV H 051310
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