LTC2232 데이터 시트보기 (PDF) - Linear Technology

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LTC2232

10-Bit,105Msps/80Msps ADCs

Linear Technology 

W

FUNCTIONAL BLOCK DIAGRA

LTC2232/LTC2233

AIN+

INPUT

AIN–

S/H

FIRST PIPELINED

ADC STAGE

SECOND PIPELINED

ADC STAGE

THIRD PIPELINED

ADC STAGE

FOURTH PIPELINED

ADC STAGE

FIFTH PIPELINED

ADC STAGE

VCM

2.2µF

1.6V

REFERENCE

RANGE

SELECT

REF

SENSE

BUF

REFH

REFL INTERNAL CLOCK SIGNALS

DIFFERENTIAL

DIFF

INPUT

CONTROL

REF

LOW JITTER

LOGIC

AMP

CLOCK

DRIVER

REFLB REFHA

0.1µF

2.2µF

1µF

REFLA REFHB

ENC+

0.1µF

1µF

ENC–

M0DE SHDN OE

Figure 1. Functional Block Diagram

SHIFT REGISTER

AND CORRECTION

OUTPUT

DRIVERS

OVDD

OF

D9

•

•

•

D0

CLKOUT

OGND

22323 F01

TI I G DIAGRA S

ANALOG

INPUT

ENC–

ENC+

D0-D9, OF

CLOCKOUT

Timing Diagram

tAP

N

N+1

tH

tL

N+2

N+3

N+4

tD

N–5

tC

N–4

N–3

N–2

N–1

22323 TD02

22323fa

13

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