MTV038N View Datasheet(PDF) - Myson Century Inc

Part Name

Description

Manufacturer

MTV038N

On-screen-display controller for CRT/LCD monitor

Myson Century Inc 

MYSON

TECHNOLOGY

MTV038

(Revision 1.1)

Fonts designed to be 12x18 display

Output display if FSS=0; first and last lines omitted

FIGURE 8. 12x18 and 12x16 Fonts

DWE - Enable double width. When the bit is set to 1, the display of OSD menu can change to half resolution

for double character width, and then the number of pixels of each line should be even. The initial value

is 0 after power up.

HSP - = 1 -> Accept positive polarity Hsync input.

= 0 -> Accept negative polarity Hsync input.

VSP - = 1 -> Accept positive polarity Vsync input.

= 0 -> Accept negative polarity Vsync input.

VCO1, VCO0 - Select the appropriate curve partitions of VCO frequency to voltage based on HFLB input and

horizontal resolution register (HORR). And there are different curve partitions based on differ-

ent application resister value on pin 3 (pin RP) as below:

(i)RRP = 5.6K ohm:

= (0, 0) -> 6MHz < Pixel rate < 24MHz

= (0, 1) -> 24MHz < Pixel rate < 48MHz

= (1, 0) -> 48MHz < Pixel rate < 96MHz

= (1, 1) -> 96MHz < Pixel rate < 128MHz

(ii)2.2K ohm < RRP < 3.3K ohm:

= (0, 0) -> 6MHz < Pixel rate < 28MHz

= (0, 1) -> 28MHz < Pixel rate < 56MHz

= (1, 0) -> 56MHz < Pixel rate < 112MHz

= (1, 1) -> 112MHz < Pixel rate < 150MHz

Notes :

Where Pixel rate = VCLK Freq = HFLB Freq * HORR * 12

The initial value is (0, 0) after power up.

1. That is, if HORR is specified and RP resister = 3.3K ohm, then (VCO1, VCO0)

= (0, 0) if 6000/(HORR * 12) < HFLB Freq (KHz) < 28000/(HORR * 12)

= (0, 1) if 28000/(HORR * 12) < HFLB Freq (KHZ) < 56000/(HORR * 12)

= (1, 0) if 56000/(HORR * 12) < HFLB Freq (KHZ) < 112000/(HORR * 12)

= (1, 1) if 112000/(HORR * 12) < HFLB Freq (KHZ) < 150000/(HORR * 12)

2. It is necessary to wait for the PLL to become stable while (i) the HORR register is being changed; (ii) the (VCO1,

VCO0) bits is changed; (iii) the horizontal signal (HFLB) is changed.

3. When PLL is unstable, don't write data in any address except Column 15,17,18 of Row 15. If data is written in any

other address, a malfunction may occur.

B7

b6

b5

b4

b3

b2

b1

b0

Column 19

-

-

-

-

-

CSR CSG CSB

Revision 1.1

-14-

2001/8/21

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