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ICS525R-11 View Datasheet(PDF) - Integrated Circuit Systems

Part Name
Description
Manufacturer
ICS525R-11
ICST
Integrated Circuit Systems ICST
ICS525R-11 Datasheet PDF : 9 Pages
1 2 3 4 5 6 7 8 9
ICS525-01/02/11/12
User Configurable Clock
Parameter
Short Circuit Current
Input Capacitance
On-chip Pull-up Resistor
Symbol
Conditions
CLK and REF outputs
CIN V, R, S pins and pin 19
RPU V, R, S pins and pin 19
Min.
Typ.
±55
4
270
Max.
Units
mA
pF
k
AC Electrical Characteristics
Unless stated otherwise, VDD = 3.3 V
Parameter
Symbol
Conditions
Input Frequency
Crystal input
FIN
Clock input
Output Clock Rise Time
0.8 to 2.0 V
Output Clock Fall Time
2.0 to 0.8 V
Output Clock Duty Cycle, OD =
2, 4, 6, 8, or 10
At VDD/2
Output Clock Duty Cycle, OD =
3, 5, 7, or 9
At VDD/2
Output Clock Duty Cycle, OD =
1 (-02 and -12 only)
At VDD/2
Power-down Time, PD low to
clocks stopped
Power-up Time, PD high to
clocks stable
Absolute Clock Period Jitter,
ICS525-01, Note 2
tja Deviation from mean
One Sigma Clock Period Jitter,
ICS525-01, Note 2
tjs
One Sigma
Absolute Clock Period Jitter,
ICS525-02, Note 2
tja Deviation from mean
One Sigma Clock Period Jitter,
ICS525-02, Note 2
tjs One Sigma
Absolute Clock Period Jitter,
ICS525-11, Note 2
tja Deviation from mean
One Sigma Clock Period Jitter,
ICS525-11, Note 2
tjs
One Sigma
Absolute Clock Period Jitter,
ICS525-12, Note 2
tja Deviation from mean
One Sigma Clock Period Jitter,
ICS525-12, Note 2
tjs
One Sigma
Min.
5
2
45
Typ.
1
1
49 to
51
Max.
27
50
55
Units
MHz
MHz
ns
ns
%
40
60
%
35
65
50
ns
10
ms
±140
ps
45
ps
±85
ps
30
ps
±160
ps
40
ps
±160
ps
40
ps
MDS 525-01/02/11/12 Q
7
Revision 101105
Integrated Circuit Systems, Inc. 525 Race Street, San Jose, CA 95126 tel (408) 297-1201 www.icst.com

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