TDA9160A/N3 View Datasheet(PDF) - Philips Electronics

Part Name

Description

Manufacturer

TDA9160A/N3

PAL/NTSC/SECAM decoder/sync processor

Philips Electronics 

Philips Semiconductors

PAL/NTSC/SECAM decoder/sync processor

Preliminary specification

TDA9160

to lock the phase 1 loop to the

incoming signal. The time constant of

the loop can be forced by the I2C-bus

(fast or slow). If required the IC can

select the time constant, depending

on the noise content of the input

signal and whether the loop is phase

locked or not (medium or slow). The

free-running frequency of the

oscillator is determined by a digital

control circuit that is locked to the

active crystal.

When a power-on-reset pulse is

detected the frequency of the

oscillator is switched to a frequency

greater than 6.75 MHz to protect the

horizontal output transistor. The

oscillator frequency is reset to

6.75 MHz when the crystal indication

bits have been loaded into the IC. To

ensure that this procedure does not

fail it is absolutely necessary to send

subaddress 00 before subaddress

01. Subaddress 00 contains the

crystal indication bits, when

subaddress 01 is received the line

oscillator calibration will be initiated.

The calibration is terminated when

the oscillator frequency reaches

6.75 MHz. The oscillator is again

calibrated when an out-of-lock

condition with the input signal is

realised by the coincidence detector.

Again the calibration will be

terminated when the oscillator

frequency reaches 6.75 MHz.

The phase 1 loop can be opened

using the I2C-bus. This is to facilitate

On Screen Display (OSD)

information. If there is no input signal

or a very noisy input signal the phase

1 loop can be opened to provide a

stable line frequency and thus a

stable picture.

The sync part provides an HA pulse

that is coupled to the processed

CVBS signal.

The horizontal drive signal can be

switched off via the I2C-bus (standby

mode). The horizontal drive is also

switched off when the over-voltage

protection circuit trips or when a POR

is detected. Should either of these

two conditions occur the IC will return

to the normal operating mode when

the appropriate command is received

via the I2C-bus. The duty cycle of the

horizontal drive signal is increased

from 2%, at start-up, to a constant

value of 55% in approximately 300

lines. The two-level sandcastle pulse

provides a combined horizontal and

vertical blanking signal and a

clamping pulse coupled to the display

section of the TV.

The vertical sawtooth generator

drives the geometry processing

circuits which provide control for the

horizontal shift, EW width, EW

parabola/width ratio, EW

corner/parabola ratio, trapezium

correction, vertical slope, vertical

shift, vertical amplitude and the

S-correction. All of these control

functions can be set via the I2C-bus.

The geometry processor has a

differential current output for the

vertical drive signal and a

single-ended output for the EW drive.

Both the vertical drive and the EW

drive outputs can be modulated for

EHT compensation. The EHT

compensation pin (pin 14) can also be

used for over-voltage protection.

De-interlace of the vertical output can

be set via the I2C-bus.

The vertical divider system has a fully

integrated vertical sync separator.

The divider can accommodate both

50 and 60 Hz systems; it can either

locate the field frequency

automatically or it can be forced to the

desired system via the I2C-bus. A

block diagram of the vertical divider

system is illustrated in Fig.4. The

divider system operates at 432 times

the horizontal line frequency. The line

counter receives enable pulses at

twice the line frequency, thereby

counting two lines per pulse.

A state diagram of the controller is

illustrated in Fig.5. Because it is

symmetrical only the right hand part

will be described.

Depending on the previously found

field frequency, the controller will be

in one of the 'count' states. When the

line counter has counted 488 pulses

(i.e. 244 lines of the video input

signal) the controller will move to the

next state depending on the output of

the norm counter. This can be either

NORM, NEAR-NORM or NO-NORM

depending on the position of the

vertical sync pulse in the previous

fields. When the counter is in the

NORM state it generates the vertical

sync pulse (VSP) automatically and

then, when the line counter is at

LC = 626, moves to the WAIT state.

In this condition it waits for the next

pulse of the double line frequency

signal and then moves to the COUNT

state of the current field frequency.

When the controller returns to the

COUNT state the line counter will be

reset half a line after the start of the

vertical sync pulse of the video input

signal.

When the controller is in the

NEAR-NORM state it will move to the

COUNT state if it detects the vertical

sync pulse within the NEAR-NORM

window (i.e. 622 < LC < 628). If no

vertical sync pulse is detected, the

controller will move back to the

COUNT state when the line counter

reaches LC = 628. The line counter

will then be reset.

When the controller is in the

NO-NORM state it will move to the

COUNT state when it detects a

vertical sync pulse and reset the line

counter. If a sync pulse is not

detected before LC = 722 (if the

phase loop is locked in forced mode)

it will move to the COUNT state and

reset the line counter. If the phase

loop is not locked the controller will

move back to the COUNT state when

LC = 628. The forced mode option

keeps the controller in either the

left-hand side (60 Hz) or the

December 1991

6

Share Link: