SA2030 View Datasheet(PDF) - South African Micro Electronic Systems
Part Name
Description
Manufacturer
SA2030 Datasheet PDF : 40 Pages
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SA9101
SA9101 REGISTER DESCRIPTION
Control Register
Default setting
After RESET, the SA9101 is initialized for PCM30 doubleframe format with register
values listed in Table 4.
Register
Name
Register Reset
ADR
Value
Meaning
CR0B[7..0]
0
00H Alarm Interrupt mode disabled/Double Violation
Detection, no influence on error counting, channel
parity alarms, data transmission via port DRO, or
synchronization. No Alarm simulation. Status register
read enabled.
CR1B[7..0]
1
C0H PCM30-doubleframe format with dual rail (RZ) line
interface ports/4 Mbps system interface mode/no AIS
CR2B[7..0]
2
transmission to remote end/Sn -bit stacks are disabled.
00H Channel Parity Check is active for channel 0.
CR3B[7..0]
3
00H Channel Loop Back and Single Frame mode are
disabled.
CR4B[7..0]
4
40H All bits of the transmitted service word are cleared (bit
2 excl.).
CR5B[7..0]
5
00H Spare bit values and additional interrupts are cleared.
CR6B[7..0]
6
00H Outputs for transmit dual rail line data and assigned
test data are active low, internal signalling stacks and
external transmit channel parity are disabled.
The Transmit Clock slot Offset is cleared.
CR7B[7..0]
7
40H 4096 kHz system clock frequency. The Transmit
Timeslot Offset is cleared.
CR8B[7..0]
8
30H Even Receive Channel Parity, Receive dual rail line
data inputs are active low. The Receive Clock slot
Offset is cleared. CRC Error Counter Extension is
disabled.
CR9B[7..0]
9
C0H The Receive Timeslot Offset is cleared.
CRAB[7..0]
A
FFH The Transmit Signalling stack is cleared. Its values
are not readable until the signalling stack mode is
enabled.
CRBB[7..0]
B
CRCB[7..0]
C
Undefined Sn bit stack contents unknown.
00H No interrupt source is enabled.
CRDB[7..0]
D
54H Idle Channel Code is set to '54' hex.
CX1B[7..0]
1
00H Half-bauded mode
CX6B[7..0]
6
00H Normal operation
CX7B[7..0]
7
00H Normal operation
CX8B[7..0]
8
00H Normal operation
CX9B[7..0]
9
00H Normal operation
Table 4: Initial Values after reset
sames
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