AD9762 View Datasheet(PDF) - Analog Devices

Part Name

Description

Manufacturer

AD9762

12-Bit, 125 MSPS TxDAC® D/A Converter

Analog Devices 

PIN CONFIGURATION

(MSB) DB11 1

28 CLOCK

DB10 2

27 DVDD

DB9 3

26 DCOM

DB8 4

25 NC

DB7 5 AD9762 24 AVDD

DB6 6 TOP VIEW 23 COMP2

DB5 7 (Not to Scale) 22 IOUTA

DB4 8

21 IOUTB

DB3 9

20 ACOM

DB2 10

19 COMP1

DB1 11

18 FS ADJ

DB0 12

17 REFIO

NC 13

16 REFLO

NC 14

15 SLEEP

NC = NO CONNECT

AD9762

PIN DESCRIPTIONS

Pin No. Name

Description

1

DB11

Most Significant Data Bit (MSB).

2–11

DB10–DB1 Data Bits 1–10.

12

DB0

Least Significant Data Bit (LSB).

13, 14, 25 NC

No Internal Connection.

15

SLEEP

Power-down Control Input. Active High. Contains active pull-down circuit, thus may be left unterminated if

not used.

16

REFLO Reference Ground when Internal 1.2 V Reference Used. Connect to AVDD to disable internal reference.

17

REFIO

Reference Input/Output. Serves as reference input when internal reference disabled (i.e., Tie REFLO to

AVDD). Serves as 1.2 V reference output when internal reference activated (i.e., Tie REFLO to ACOM).

Requires 0.1 µF capacitor to ACOM when internal reference activated.

18

FS ADJ Full-Scale Current Output Adjust.

19

COMP1 Bandwidth/Noise Reduction Node. Add 0.1 µF to AVDD for optimum performance.

20

ACOM Analog Common.

21

IOUTB Complementary DAC Current Output. Full-scale current when all data bits are 0s.

22

IOUTA DAC Current Output. Full-scale current when all data bits are 1s.

23

COMP2 Internal Bias Node for Switch Driver Circuitry. Decouple to ACOM with 0.1 µF capacitor.

24

AVDD

Analog Supply Voltage (+2.7 V to +5.5 V).

26

DCOM Digital Common.

27

DVDD

Digital Supply Voltage (+2.7 V to +5.5 V).

28

CLOCK Clock Input. Data latched on positive edge of clock.

REV. B

–5–

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