A75 View Datasheet(PDF) - Intel

Part Name

Description

Manufacturer

A75

PENTIUM® PROCESSOR

Intel 

E

PENTIUM® PROCESSOR 75/90/100/120/133/150/166/200

Table 2. Quick Pin Reference (Continued)

Symbol

Type*

Name and Function

SMIACT#

O

An active system management interrupt active output indicates that the

processor is operating in System Management Mode.

STPCLK#

I

Assertion of the stop clock input signifies a request to stop the internal clock of

the Pentium processor 75/90/100/120/133/150/166/200 thereby causing the core to

consume less power. When the CPU recognizes STPCLK#, the processor will

stop execution on the next instruction boundary, unless superseded by a higher

priority interrupt, and generate a stop grant acknowledge cycle. When STPCLK#

is asserted, the Pentium processor 75/90/100/120/133/150/166/200 will still

respond to interprocessor and external snoop requests.

TCK

I

The testability clock input provides the clocking function for the Pentium

processor 75/90/100/120/133/150/166/200 boundary scan in accordance with the

IEEE Boundary Scan interface (Standard 1149.1). It is used to clock state

information and data into and out of the Pentium processor 75/90/100/120/133/150/

166/200 during boundary scan.

TDI

I

The test data input is a serial input for the test logic. TAP instructions and data

are shifted into the Pentium processor 75/90/100/120/133/150/166/200 on the TDI

pin on the rising edge of TCK when the TAP controller is in an appropriate state.

TDO

O

The test data output is a serial output of the test logic. TAP instructions and data

are shifted out of the Pentium processor 75/90/100/120/133/150/166/200 on the

TDO pin on TCK's falling edge when the TAP controller is in an appropriate state.

TMS

I

The value of the test mode select input signal sampled at the rising edge of TCK

controls the sequence of TAP controller state changes.

TRST#

I

When asserted, the test reset input allows the TAP controller to be

asynchronously initialized.

VCC

I

The Pentium processor 75/90/100/120/133/150/166/200 has 53 3.3V power

inputs.

VSS

I

The Pentium processor 75/90/100/120/133/150/166/200 has 53 ground inputs.

W/R#

O

Write/read is one of the primary bus cycle definition pins. It is driven valid in the

same clock as the ADS# signal is asserted. W/R# distinguishes between write

and read cycles.

WB/WT#

I

The write back/write through input allows a data cache line to be defined as

write back or write through on a line-by-line basis. As a result, it determines

whether a cache line is initially in the S or E state in the data cache.

NOTE:

• The pins are classified as Input or Output based on their function in Master Mode. See the Functional Redundancy

Checking section in the “Error Detection” chapter of the Pentium® Processor Family Developer’s Manual, Volume 1, for

further information.

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