Philips Semiconductors
Poseidon embedded processor
MEMORY INTERFACE TIMING DIAGRAMS
DCLKOUT
1
2
MEMORY
OUTPUTS
3
4
Figure 1. Memory Output and Clock Timing
DCLKIN
MEMORY
INPUTS
5
6
Figure 2. Memory Input Timing
DCLKOUT
DCLKIN
7
Figure 3. DCLKOUT to DCLKIN
Preliminary specification
MIPS
PR31500
SN00168
SN00169
SN00170
1996 Sep 24
16