AD9226 View Datasheet(PDF) - Analog Devices

Part Name

Description

Manufacturer

AD9226

Complete 12-Bit, 65 MSPS ADC Converter

Analog Devices 

AD9226

DEFINITIONS OF SPECIFICATIONS

INTEGRAL NONLINEARITY (INL)

INL refers to the deviation of each individual code from a line

drawn from “negative full scale” through “positive full scale.”

The point used as “negative full scale” occurs 1/2 LSB before

the first code transition. “Positive full scale” is defined as a level

1 1/2 LSB beyond the last code transition. The deviation is

measured from the middle of each particular code to the true

straight line.

DIFFERENTIAL NONLINEARITY (DNL, NO MISSING

CODES)

An ideal ADC exhibits code transitions that are exactly 1 LSB

apart. DNL is the deviation from this ideal value. Guaranteed

no missing codes to 12-bit resolution indicates that all 4096

codes, respectively, must be present over all operating ranges.

ZERO ERROR

The major carry transition should occur for an analog value

1/2 LSB below VINA = VINB. Zero error is defined as the

deviation of the actual transition from that point.

GAIN ERROR

The first code transition should occur at an analog value

1/2 LSB above negative full scale. The last transition should

occur at an analog value 1 1/2 LSB below the positive full scale.

Gain error is the deviation of the actual difference between first

and last code transitions and the ideal difference between first

and last code transitions.

TEMPERATURE DRIFT

The temperature drift for zero error and gain error specifies the

maximum change from the initial (25°C) value to the value at

TMIN or TMAX.

POWER SUPPLY REJECTION

The specification shows the maximum change in full scale from

the value with the supply at the minimum limit to the value with

the supply at its maximum limit.

APERTURE JITTER

Aperture jitter is the variation in aperture delay for successive

samples and can be manifested as noise on the input to the ADC.

APERTURE DELAY

Aperture delay is a measure of the sample-and-hold amplifier

(SHA) performance and is measured from the rising edge of the

clock input to when the input signal is held for conversion.

SIGNAL-TO-NOISE AND DISTORTION (S/N+D, SINAD)

RATIO

S/N+D is the ratio of the rms value of the measured input

signal to the rms sum of all other spectral components below

the Nyquist frequency, including harmonics but excluding dc.

The value for S/N+D is expressed in decibels.

EFFECTIVE NUMBER OF BITS (ENOB)

For a sine wave, SINAD can be expressed in terms of the num-

ber of bits. Using the following formula,

N = (SINAD – 1.76)/6.02

it is possible to obtain a measure of performance expressed as

N, the effective number of bits.

Thus, effective number of bits for a device for sine wave inputs

at a given input frequency can be calculated directly from its

measured SINAD.

TOTAL HARMONIC DISTORTION (THD)

THD is the ratio of the rms sum of the first six harmonic com-

ponents to the rms value of the measured input signal and is

expressed as a percentage or in decibels.

SIGNAL-TO-NOISE RATIO (SNR)

SNR is the ratio of the rms value of the measured input signal to

the rms sum of all other spectral components below the Nyquist

frequency, excluding the first six harmonics and dc. The value

for SNR is expressed in decibels.

SPURIOUS FREE DYNAMIC RANGE (SFDR)

SFDR is the difference in dB between the rms amplitude of the

input signal and the peak spurious signal.

ENCODE PULSEWIDTH DUTY CYCLE

Pulsewidth high is the minimum amount of time that the clock

pulse should be left in the logic “1” state to achieve rated per-

formance; pulsewidth low is the minimum time the clock pulse

should be left in the low state. At a given clock rate, these specs

define an acceptable clock duty cycle.

MINIMUM CONVERSION RATE

The clock rate at which the SNR of the lowest analog signal

frequency drops by no more than 3 dB below the guaranteed limit.

MAXIMUM CONVERSION RATE

The encode rate at which parametric testing is performed.

OUTPUT PROPAGATION DELAY

The delay between the clock logic threshold and the time when

all bits are within valid logic levels.

TWO TONE SFDR

The ratio of the rms value of either input tone to the rms value

of the peak spurious component. The peak spurious component

may or may not be an IMD product. May be reported in dBc

(i.e., degrades as signal levels are lowered) or in dBFS (always

related back to converter full scale).

REV. B

–7–

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