A8259 View Datasheet(PDF) - Altera Corporation
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A8259 Datasheet PDF : 24 Pages
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a8259 Programmable Interrupt Controller Data Sheet
Table 1 describes the input and output ports of the a8259.
Table 1. a8259 Ports
Name
Type Polarity
Description
nmrst
clk
ncs
nwr
nrd
a0
ninta
nsp
casin[2..0]
ir[7..0]
din[7..0]
int
casout[2..0]
cas_en
dout[7..0]
nen
Input
Input
Input
Input
Input
Input
Input
Input
Input
Inputs
Input
Output
Output
Output
Output
Output
Low
–
Low
Low
Low
High
Low
Low
High
High (1)
–
High
High
High
–
Low
Master reset. When nmrst is asserted, all internal registers assume their
default state. The a8259 is idle, awaiting initialization.
Clock. All registers are clocked on the positive edge of the clock.
Chip select. When low, this signal enables the nwr and nrd signals and
register access to and from the a8259.
Write control. When this signal is low (and ncs signal is also low), it enables
write transactions to the a8259.
Read control. When this signal is low (and ncs signal is also low), it enables
read transactions from the a8259.
Address. This signal serves as a register selector when writing to and
reading from internal a8259 registers.
Interrupt acknowledge. This signal serves as the primary handshake
between the a8259 and microprocessor during an interrupt service cycle.
Slave processor. This signal indicates that the a8259 should be configured
as a slave. However, this signal is ignored when the a8259 is configured
as a single device. This signal should also be ignored in buffered mode.
Cascade data bus. These bus signals act as a cascade mode control to a
slave a8259. If the a8259 is configured as a master, the bus should be
driven low.
Interrupt request. These are eight maskable, prioritized interrupt service
request signals.
Data bus. This bus inputs data when writing to internal a8259 registers.
Interrupt. This signal indicates that the a8259 has made an unmasked
service request.
Cascade data bus. These bus signals act as cascade mode control, and
should be connected to the casin[2..0] bus of a slave a8259. When
the a8259 is configured as a master, the casout[2..0]bus is ignored.
Cascade directional bus enable. This signal is intended as a tri-state enable
signal to external bidirectional I/O buffers on the cascade control bus.
Data bus. The output data when reading from internal a8259 registers.
Data enable. This signal indicates that a read cycle is being performed on
an internal a8259 register, and it is intended as a tri-state enable to
external bidirectional I/O buffers.
Note:
(1) The interrupt request signals can be set as active high or positive-edge-triggered via bit 3 of Initialization Command
Word (ICW) 1 (see “ICW 1” on page 62 for more information).
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