A8259 View Datasheet(PDF) - Altera Corporation
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A8259 Datasheet PDF : 24 Pages
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a8259 Programmable Interrupt Controller Data Sheet
ICW 3
If SINGLE is low, ICW 3 must be initialized. Input data for ICW 3 is sent
via the din[7..0] bus, and data is clocked by the rising edge of clk.
ICW 3 is deselected with the next falling edge of the nwr signal.
The meaning of the ICW 3 contents depends on whether the a8259 is
configured as a master or slave. Table 5 describes the ICW 3 register
format for the a8259 configured as a master.
Table 5. ICW 3 Register Format (a8259 Master Configuration)
Bit Mnemonic
Description
0
S0
These bits are slave inputs. When high, each bit
1
S1
indicates that the corresponding interrupt request line is
2
S2
a cascaded slave input. For instance, if S2 is high, the
3
S3
ir2 pin is treated as a slave input and receives data
from the int signal of another a8259.
4
S4
5
S5
6
S6
7
S7
Table 6 describes the ICW 3 register format when the a8259 is configured
as a slave.
Table 6. ICW 3 Register Format (a8259 Slave Configuration)
Bit Mnemonic
Description
0
ID0
Slave identification. These bits set the slave ID for the
1
ID1
a8259.
2
ID2
3
0
These bits are not used when the a8259 is configured
4
0
as a slave, and they should be low.
5
0
6
0
7
0
At this point in the initialization process, the next register selected
depends on whether bit 0 of ICW 1 is high. If bit 0 of ICW 1 is high, ICW 4
is selected (see “ICW 4” on page 65). If bit 0 is low, ICW 4 is skipped and
the a8259 is ready to accept interrupts.
64
Altera Corporation
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