EL7571C View Datasheet(PDF) - Elantec -> Intersil

Part Name

Description

Manufacturer

EL7571C

Programmable PWM Controller

Elantec -> Intersil 

EL7571C

Programmable PWM Controller

voltage, inductor current is prevented from ramping to a

high level in the reverse direction. This prevents the par-

asitic boost action of the local power supply when the

fault is removed and potential damage to circuitry con-

nected to the local supply.

Oscillator

A system clock is generated by an internal relaxation

oscillator. Operating frequency is simple to adjust using

a single external capacitor COSC. The ratio of charge to

discharge current in the oscillator is well defined and

sets the maximum duty cycle for the system at around

96%.

Soft-start

During start-up, potentially large currents can flow into

the regulator output capacitors due to the fast rate of

change of output voltage caused during start-up,

although peak inrush current will be limited by the over

current comparator. However an additionally internal

switch capacitor soft-start circuit controls the rate of

change of output voltage during start-up by overriding

the voltage feedback input of the main summing com-

parator, limiting the start-up ramp to around 1ms under

typical operating conditions. The soft-start ramp is reset

whenever the output enable (OUTEN) is reset or when-

ever the controller supply falls below 3.5V.

Watchdog

A system watchdog monitors the condition of the con-

troller supply and the integrity of the generated output

voltage. Modern logic level power FET’s rapidly

increase in resistivity (Rdson) as their gate drive is

reduced below 5V. To prevent thermal damage to the

power FET’s under load, with a reduced supply voltage,

the system watchdog monitors the controller supply

(VIN) and disables both PWM outputs (HSD, LSD)

when the supply voltage drops below 3.5V. When the

supply voltage is increased above 4V the watchdog ini-

tiates a soft-start ramp and enables PWM operation. The

difference between enable and disable thresholds intro-

duces hysteresis into the circuit operation, preventing

start-up oscillation. In addition, output voltage is also

monitored by the watchdog. As called out by the Intel

Pentium® II VRM specification, the watchdog power

good output (PWRGD) is set low whenever the output

voltage differs from it’s selected value by more than

±13%. PWRGD is an open drain output. A third watch-

dog function disables PWM output switching during

over-voltage fault conditions, displaying both external

FET drives, whenever the output voltage is greater than

13% of its selected value, thereby anticipating reverse

inductor current ramping and conforming to the VRM

over-voltage specification, which requires the regulator

output to be disabled during fault conditions. Switching

is enabled after the fault condition is removed.

Output Drivers

Complementary control signals developed by the PWM

control loop are fed to dual NMOS power FET drivers

via a level shift circuit. Each driver is capable of deliver-

ing nominal peak output currents of 2A at 12V. To

prevent shoot-through in the external FET’s, each driver

is disabled until the gate voltage of the complementary

power FET has fallen to less than 1V. Supply connec-

tions for both drivers are independent, allowing the

controller to be configured with a boot-strapped high

side drive. Employing this technique a single supply

voltage may be used for both power FET’s and control-

ler. Alternatively, the application may be simplified

using dual supply rails with the power FET’s connected

to a secondary supply voltage below the controller’s,

typically 12V and 5V. For applications where efficiency

is less important than cost, applications can be further

simplified by replacing the low side power FET with a

Schottky diode, resulting in non-synchronous operation.

Applications Information

The EL7571C is designed to meet the Intel 5 bit VRM

specification. Refer to the VID decode table for the con-

troller output voltage range.

The EL7571C may be used in a number converter topol-

ogies. The trade-off between efficiency, cost, circuit

complexity, line input noise, transient response and

availability of input supply voltages will determine

which converter topology is suitable for a given applica-

8

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