CA3098 View Datasheet(PDF) - Intersil
Part Name
Description
Manufacturer
CA3098 Datasheet PDF : 12 Pages
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CA3098
General Description of Circuit Operation
When the signal input voltage of the CA3098 is equal to or
less than the “low” reference voltage (LR), current flows from
an external power supply through a load connected to
Terminal 3 (“sink” output). This condition is maintained until
the signal input voltage rises to or exceeds the “high”
reference voltage (HR), thereby effecting a change in the
state of the flip-flop (memory) such that the output stage
interrupts current flow in the external load. This condition, in
turn, is maintained until such time as the signal again
becomes equal to or less than the “low” reference voltage.
The CA3098 comparator is unique in that it contains circuit
provisions to permit programmability. This feature provides
flexibility to the designer to optimize quiescent power
consumption, input circuit characteristics, hysteresis, and
additionally permits independent control of the comparator,
namely, pulsing, strobing, keying, squelching, etc.
Programmability is accomplished by means of the bias
current (IBIAS) supplied to Terminal 2.
An auxiliary means of controlling the magnitude of load
current flow at Terminal 3 is provided by “sinking” current into
Terminal 5. Figure 1 highlights the operation of the CA3098
when connected as a simple hysteresis switch (Schmitt
trigger).
INPUT
SIGNAL
EIN
120kΩ
RB
2
“HIGH” REF. = 8V
6
7
5
8
CA3098
1
“LOW” REF. = 4V
4
V+ = 12VDC
IO
RL
3 EO
SEQUENCE
1
2
3
2
1
INPUT SIGNAL
LEVEL
4 ≥ EIN > 0
8 ≥ EIN > 4
EIN > 8
8 ≥ EIN > 4
4 ≥ EIN > 0
OUTPUT VOLTAGE (V)
(TERMINAL 3)
0
0
12
12
0
FIGURE 1. BASIC HYSTERESIS SWITCH (SCHMITT
TRIGGER) AND RESULTANT OUTPUT STATES
Metallization Mask Layout
0
61 60
10 20 30 40 50 58
50
Dimensions in parentheses are in millimeters and are derived
40
from the basic inch dimensions as indicated. Grid graduations
are in mils (10-3 inch).
30
66 (1.676) The layout represents a chip when it is part of the wafer. When
the wafer is cut into chips, the cleavage angles are 57o instead
of 90o with respect to the face of the chip. Therefore, the
20
isolated chip is actually 7mils (0.17mm) larger in both
dimensions.
10
0
63 (1.600)
4
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