STV0299B View Datasheet(PDF) - STMicroelectronics
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STV0299B Datasheet PDF : 36 Pages
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STV0299B
4 FUNCTIONAL DESCRIPTION (continued)
4.1.9 Clock Registers
The Reference Clock, Master Clock, Auxiliary
Clock and F22 Frequency Registers are in
Addresses 01, 02, 03 and 04.
4.1.10 I2C Bus Repeater
In low symbol rate applications, signal pollution
generated by the SDA/SCL lines of the I2C bus
may dramatically worsen tuner phase noise. In
order to avoid this problem, the STV0299B offers
an I2C bus repeater so that the SDAT and SCLT
are active only when necessary and muted once
the tuner frequency has settled.
Both SDAT and SCLT pins are set high at reset.
When the microprocessor writes a 1 into register
bit I2CT, the next I2C message on SDA and SCL is
repeated on the SDAT and SCLT pins respectively,
until stop conditions are detected.
To write to the tuner, the external microprocessor
must, for each tuner message, perform the
following:
• Program 1 in I2CT.
• Send the message to the tuner.
Any size of byte transfers are allowed, regardless
of the address, until the stop conditions are
detected. Transfers are fully bi-directional.
The I2CT bit is automatically reset at the stop
condition. If not used for the I2C repeater, both
SDAT and SCLT outputs may be used as general
purpose output ports.
SDAT status may be read on the DiSEqC register.
Configuration is controlled by the I2C repeater
register in Address 0Ah.
In the first version of the STV0299, operation of
the repeater was very fast, and often too fast
versus the rise time of the SDAT and SCLT
signals. In the STV0299B, a programmable delay
is implemented to accept a wide range of rise
times on SDAT and SCLT. The delay is
programmed with Reg.05 [5:4]. In practice,
operation of the repeater is ensured in the
following case:
• Reg.05 [5:4]: xx
• fM_CLK ≤ 90 MHz
• RC≤ 250ns (R: pull-up resistor, C: total
capacitance on either SDAT or SCLT).
4.1.11 General Purpose Σ∆ DAC
A DAC is available in order to control external
analog devices. It is built as a sigma-delta
first-order loop, and has 12-bit resolution-it only
requires an external low-pass filter (simple RC
filter). The clock frequency is derived from the
main clock by programmable division. The
converter is controlled by two registers-one for
10/36
clock divider control and 4 MSBs, and the other for
the 8 LSBs.
If the DAC is not needed, the DAC output may be
used as an output port. The DAC Registers are in
Addresses 06 and 07.
4.1.12 DiSEqC Interface
This interface allows for the simplification of real
time processing of the dialog from microprocessor
to LNB. It includes a FIFO that is filled by the
microprocessor via the I2C bus, and then
transmitted by modulating the F22 clock adjusted
beforehand to 22 kHz.
Two control signals are available on the I2C bus:
FE (FIFO empty) and FF (FIFO full).
A typical byte transfer loop, as seen from the
microprocessor, may be the following:
While (there is data to transfer)
1 Read the control signals
2 If FF=1, go to 1
3 Write byte to transfer in the FIFO
Note, for the above transfer loop, the following:
• At the beginning, the FIFO is empty (FE=1,
FF=0). This is the idle state.
• As soon as a byte is written in the FIFO, the
transfer will begin.
• After the last transmitted byte, the interface will
go into the idle state.
Modulation
The output is a gated 22 kHz square signal.
• In the idle state, modulation is permanently
inactive.
• In byte transmission, the byte is sent (MSB
first) and is followed by an odd parity bit.
A byte transmission is therefore a serial 9-bit
transmission with an odd number of “1’s”.
Each bit lasts 33 periods of F22 and the
transmission is PWM-modulated.
- Transmission of “0’s”. There are two
submodes controlled by PortCtrl(2):
a) PortCtrl2 = 1: Modulation is active during
22 pulses, then inactive during 11 pulses
(2/3 PWM).
b) PortCtrl2 = 0: Modulation is active during
33 pulses (3/3 PWM).
- Transmission of “1’s”. During transmission
of “1’s”, modulation is active during 11 pulses,
then inactive during 22 pulses (1/3 PWM).
This is compatible with “Tone Burst” in older LNB
protocols.
For the “Modulated Tone Burst”, only one byte
(with value Hex FF) is written in the FIFO.
The parity bit is 1, and as a result, the output
signal is 9 bursts of 0.5 ms, separated by
8 intervals of 1 ms.
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