STV0299B View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

STV0299B

QPSK/BPSK LINK IC

STMicroelectronics 

STV0299B

4 FUNCTIONAL DESCRIPTION (continued)

4.1.5 Specific Concerns about SCL

Frequency

For reliable operation in Normal Mode, the SCL

frequency must be lower than 1/40 of the Master

Clock (M_CLK) frequency. Consequently, care

should be taken to observe the following:

1 Before returning to Normal Mode from Standby

Mode, the M_CLK frequency must be selected

such that fM_CLK ≥ 40 fSCL

2 After Power-on reset signal, the STV0299B

operates in Normal Mode. There are two possi-

ble cases:

- DIRCLK-DIS (pin 58) is grounded.

M_CLK = CLK_IN, the fSCL frequency of the

. I2C bus must satisfy:

fSCL

≤

C-----L---K----_---I--N---

40

- DIRCLK-DIS (pin 58) is tied to VDD

(where

f M_CLK

=

1----0---0--

16

⋅

fCLK_IN),

and

the

fSCL

frequency of the I2C bus must satisfy:

fSCL ≤ 1----6-1----×0---0-4----0-- ⋅ CLK_IN and fSCL ≤ 400 kHz.

For example, this second operating mode is

required when the application features both a

4 MHz XTAL and a 400 kHz I2C bus.

4.1.6 Identification Register

The Identification Register (at address Hex 00)

gives the release number of the circuit.

The content of this register at reset is presently A1

(same as STV0299).

4.1.7 Sampling Frequency

The STV0299B converts the analog inputs into

digital 6-bit I and Q flows. The sampling frequency

is fM_CLK which is derived from an external

reference described in Section 4.1.8 ‘Clock

Generation’. The maximum value of fM_CLK is 90

MHz.

The sampling causes the repetition of the input

spectrum at each integer multiple of fM_CLK. One

has to ensure that no frequency component is

folded in the useful signal bandwidth of fS(1+α)/2

where fS is the symbol frequency, and α is the

roll-off value.

4.1.8 Clock Generation

An integrated VCO (optimised to run in the range

of 300 to 400 MHz) is locked to a reference

frequency provided by a crystal oscillator by the

following relation:

fVCO

=

fref ⋅ 4 ⋅ (M + 1)

=

fX

TA

L

⋅

4

⋅

-M------+-----1--

K+1

The VCO’s loop filter is optimized for a reference

frequency between 4 and 8 MHz.

The VCO generates the following by division:

• The Master Clock (M_CLK)

• An auxiliary clock (AUX_CLK) which may either

be in the MHz range or in the 25 Hz to 1500 Hz

range for some specific LNB control (for

example, 60 Hz).

• A lower frequency, F22, typically 22 KHz,

needed for LNB control or DiSEqCTM control.

When DIRCLK_CTRL = 1, the crystal signal is

routed directly to M_CLK; the VCO may still be

used to generate AUX_CK and/or the F22 (used

by the DiSEqCTM interface).

If the internal VCO is not used by any of the

dividers, it may be stopped in order to decrease

the power consumption and/or radiation

emissions. The only guaranteed function in

standby mode is the I2C Write/Read function of

the three clock control registers.

There are restrictions on the high and low level

durations, and on the crystal (or external clock)

frequency when the direct clock is used.

These restrictions are explained in Section 4.1.5

Specific Concerns about SCL Frequency.

8/36

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